//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
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//-----------------------------------------------------------------------------
//
// Project    : Ultrascale FPGA Gen3 Integrated Block for PCI Express
// File       : xdma_x8gen3_pcie3_ip_pcie3_uscale_top.v
// Version    : 4.4 
//-----------------------------------------------------------------------------

/////////////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps

module xdma_x8gen3_pcie3_ip_pcie3_uscale_top 
 #(
  parameter TCQ = 100,
  parameter NO_DECODE_LOGIC  = "TRUE",
  parameter INTERFACE_SPEED  = "500MHZ",
  parameter COMPLETION_SPACE = "16KB",
  parameter KEEP_WIDTH = 8,
  parameter C_DATA_WIDTH = 256,
  parameter PIPE_PIPELINE_STAGES = 0,
  parameter ARI_CAP_ENABLE = "FALSE",
  parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
  parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE",
  parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
  parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE",
  parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000,
  parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE",
  parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
  parameter AXISTEN_IF_RC_STRADDLE = "FALSE",
  parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
  parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE",
  parameter [1:0] AXISTEN_IF_WIDTH = 2'h2,
  parameter CRM_CORE_CLK_FREQ_500 = "TRUE",
  parameter [1:0] CRM_USER_CLK_FREQ = 2'h2,
  parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE",
  parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
  parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE",
  parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
  parameter [8:0] LL_ACK_TIMEOUT = 9'h000,
  parameter LL_ACK_TIMEOUT_EN = "FALSE",
  parameter integer LL_ACK_TIMEOUT_FUNC = 0,
  parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000,
  parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
  parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000,
  parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
  parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000,
  parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
  parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000,
  parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
  parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000,
  parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
  parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
  parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0fa,
  parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE",
  parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE",
  parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000,
  parameter MCAP_CONFIGURE_OVERRIDE = "FALSE",
  parameter MCAP_ENABLE = "FALSE",
  parameter MCAP_EOS_DESIGN_SWITCH = "TRUE",
  parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000,
  parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "TRUE",
  parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "TRUE",
  parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE",
  parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE",
  parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE",
  parameter [15:0] MCAP_VSEC_ID = 16'h0000,
  parameter [11:0] MCAP_VSEC_LEN = 12'h02c,
  parameter [3:0] MCAP_VSEC_REV = 4'h0,
  parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
  parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
  parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000,
  parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00,
  parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000,
  parameter [3:0] PF0_ARI_CAP_VER = 4'h1,
  parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03,
  parameter [2:0] PF0_BAR0_CONTROL = 3'h4,
  parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00,
  parameter [2:0] PF0_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_BAR5_CONTROL = 3'h0,
  parameter [7:0] PF0_BIST_REGISTER = 8'h00,
  parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50,
  parameter [23:0] PF0_CLASS_CODE = 24'h000000,
  parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
  parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0,
  parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
  parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE",
  parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
  parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE",
  parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE",
  parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE",
  parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0,
  parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE",
  parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
  parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
  parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE",
  parameter [15:0] PF0_DEVICE_ID = 16'h0000,
  parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
  parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
  parameter [3:0] PF0_DPA_CAP_VER = 4'h1,
  parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10c,
  parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
  parameter PF0_EXPANSION_ROM_ENABLE = "FALSE",
  parameter [7:0] PF0_INTERRUPT_LINE = 8'h00,
  parameter [2:0] PF0_INTERRUPT_PIN = 3'h1,
  parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7,
  parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
  parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000,
  parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000,
  parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000,
  parameter [3:0] PF0_LTR_CAP_VER = 4'h1,
  parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0,
  parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00,
  parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE",
  parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00,
  parameter integer PF0_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer PF0_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000,
  parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
  parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000,
  parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
  parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000,
  parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
  parameter [3:0] PF0_PB_CAP_VER = 4'h1,
  parameter [7:0] PF0_PM_CAP_ID = 8'h01,
  parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00,
  parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE",
  parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE",
  parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE",
  parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE",
  parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3,
  parameter PF0_PM_CSR_NOSOFTRESET = "TRUE",
  parameter PF0_RBAR_CAP_ENABLE = "FALSE",
  parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000,
  parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000,
  parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000,
  parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000,
  parameter [3:0] PF0_RBAR_CAP_VER = 4'h1,
  parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0,
  parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0,
  parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0,
  parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00,
  parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00,
  parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00,
  parameter [2:0] PF0_RBAR_NUM = 3'h1,
  parameter [7:0] PF0_REVISION_ID = 8'h00,
  parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4,
  parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
  parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0,
  parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000,
  parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000,
  parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000,
  parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1,
  parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000,
  parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000,
  parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
  parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000,
  parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000,
  parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter PF0_TPHR_CAP_ENABLE = "FALSE",
  parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] PF0_TPHR_CAP_VER = 4'h1,
  parameter PF0_VC_CAP_ENABLE = "FALSE",
  parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000,
  parameter [3:0] PF0_VC_CAP_VER = 4'h1,
  parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
  parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
  parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000,
  parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00,
  parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000,
  parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03,
  parameter [2:0] PF1_BAR0_CONTROL = 3'h4,
  parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00,
  parameter [2:0] PF1_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_BAR5_CONTROL = 3'h0,
  parameter [7:0] PF1_BIST_REGISTER = 8'h00,
  parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50,
  parameter [23:0] PF1_CLASS_CODE = 24'h000000,
  parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
  parameter [15:0] PF1_DEVICE_ID = 16'h0000,
  parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
  parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
  parameter [3:0] PF1_DPA_CAP_VER = 4'h1,
  parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10c,
  parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
  parameter PF1_EXPANSION_ROM_ENABLE = "FALSE",
  parameter [7:0] PF1_INTERRUPT_LINE = 8'h00,
  parameter [2:0] PF1_INTERRUPT_PIN = 3'h1,
  parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0,
  parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00,
  parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE",
  parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00,
  parameter integer PF1_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer PF1_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000,
  parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
  parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000,
  parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
  parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000,
  parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
  parameter [3:0] PF1_PB_CAP_VER = 4'h1,
  parameter [7:0] PF1_PM_CAP_ID = 8'h01,
  parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3,
  parameter PF1_RBAR_CAP_ENABLE = "FALSE",
  parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000,
  parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000,
  parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000,
  parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000,
  parameter [3:0] PF1_RBAR_CAP_VER = 4'h1,
  parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0,
  parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0,
  parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0,
  parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00,
  parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00,
  parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00,
  parameter [2:0] PF1_RBAR_NUM = 3'h1,
  parameter [7:0] PF1_REVISION_ID = 8'h00,
  parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4,
  parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
  parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0,
  parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000,
  parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000,
  parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000,
  parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1,
  parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000,
  parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000,
  parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
  parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000,
  parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000,
  parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter PF1_TPHR_CAP_ENABLE = "FALSE",
  parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] PF1_TPHR_CAP_VER = 4'h1,
  parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
  parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
  parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000,
  parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00,
  parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000,
  parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03,
  parameter [2:0] PF2_BAR0_CONTROL = 3'h4,
  parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00,
  parameter [2:0] PF2_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_BAR5_CONTROL = 3'h0,
  parameter [7:0] PF2_BIST_REGISTER = 8'h00,
  parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50,
  parameter [23:0] PF2_CLASS_CODE = 24'h000000,
  parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
  parameter [15:0] PF2_DEVICE_ID = 16'h0000,
  parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
  parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
  parameter [3:0] PF2_DPA_CAP_VER = 4'h1,
  parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10c,
  parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
  parameter PF2_EXPANSION_ROM_ENABLE = "FALSE",
  parameter [7:0] PF2_INTERRUPT_LINE = 8'h00,
  parameter [2:0] PF2_INTERRUPT_PIN = 3'h1,
  parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0,
  parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00,
  parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE",
  parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00,
  parameter integer PF2_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer PF2_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000,
  parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
  parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000,
  parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
  parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000,
  parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
  parameter [3:0] PF2_PB_CAP_VER = 4'h1,
  parameter [7:0] PF2_PM_CAP_ID = 8'h01,
  parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3,
  parameter PF2_RBAR_CAP_ENABLE = "FALSE",
  parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000,
  parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000,
  parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000,
  parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000,
  parameter [3:0] PF2_RBAR_CAP_VER = 4'h1,
  parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0,
  parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0,
  parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0,
  parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00,
  parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00,
  parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00,
  parameter [2:0] PF2_RBAR_NUM = 3'h1,
  parameter [7:0] PF2_REVISION_ID = 8'h00,
  parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4,
  parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
  parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0,
  parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000,
  parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000,
  parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000,
  parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1,
  parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000,
  parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000,
  parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
  parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000,
  parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000,
  parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter PF2_TPHR_CAP_ENABLE = "FALSE",
  parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] PF2_TPHR_CAP_VER = 4'h1,
  parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
  parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
  parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000,
  parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00,
  parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000,
  parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03,
  parameter [2:0] PF3_BAR0_CONTROL = 3'h4,
  parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00,
  parameter [2:0] PF3_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_BAR5_CONTROL = 3'h0,
  parameter [7:0] PF3_BIST_REGISTER = 8'h00,
  parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50,
  parameter [23:0] PF3_CLASS_CODE = 24'h000000,
  parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
  parameter [15:0] PF3_DEVICE_ID = 16'h0000,
  parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
  parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
  parameter [3:0] PF3_DPA_CAP_VER = 4'h1,
  parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10c,
  parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
  parameter PF3_EXPANSION_ROM_ENABLE = "FALSE",
  parameter [7:0] PF3_INTERRUPT_LINE = 8'h00,
  parameter [2:0] PF3_INTERRUPT_PIN = 3'h1,
  parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0,
  parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00,
  parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE",
  parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00,
  parameter integer PF3_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer PF3_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000,
  parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
  parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000,
  parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
  parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000,
  parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
  parameter [3:0] PF3_PB_CAP_VER = 4'h1,
  parameter [7:0] PF3_PM_CAP_ID = 8'h01,
  parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3,
  parameter PF3_RBAR_CAP_ENABLE = "FALSE",
  parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000,
  parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000,
  parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000,
  parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000,
  parameter [3:0] PF3_RBAR_CAP_VER = 4'h1,
  parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0,
  parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0,
  parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0,
  parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00,
  parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00,
  parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00,
  parameter [2:0] PF3_RBAR_NUM = 3'h1,
  parameter [7:0] PF3_REVISION_ID = 8'h00,
  parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4,
  parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
  parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0,
  parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000,
  parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000,
  parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000,
  parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1,
  parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000,
  parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000,
  parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
  parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000,
  parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000,
  parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter PF3_TPHR_CAP_ENABLE = "FALSE",
  parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] PF3_TPHR_CAP_VER = 4'h1,
  parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE",
  parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE",
  parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
  parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE",
  parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "FALSE",
  parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE",
  parameter PL_DISABLE_SCRAMBLING = "FALSE",
  parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE",
  parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE",
  parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE",
  parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE",
  parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02,
  parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1,
  parameter PL_EQ_BYPASS_PHASE23 = "FALSE",
  parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3,
  parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4,
  parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE",
  parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE",
  parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3f00,
  parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4,
  parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8,
  parameter integer PL_N_FTS_COMCLK_GEN1 = 255,
  parameter integer PL_N_FTS_COMCLK_GEN2 = 255,
  parameter integer PL_N_FTS_COMCLK_GEN3 = 255,
  parameter integer PL_N_FTS_GEN1 = 255,
  parameter integer PL_N_FTS_GEN2 = 255,
  parameter integer PL_N_FTS_GEN3 = 255,
  parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE",
  parameter PL_SIM_FAST_LINK_TRAINING = "TRUE",
  parameter PL_UPSTREAM_FACING = "TRUE",
  parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05dc,
  parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000,
  parameter PM_ENABLE_L23_ENTRY = "FALSE",
  parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE",
  parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000,
  parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186a0,
  parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064,
  parameter SIM_JTAG_IDCODE = 32'h00000000,
  parameter SIM_VERSION = "1.0",
  parameter integer SPARE_BIT0 = 0,
  parameter integer SPARE_BIT1 = 0,
  parameter integer SPARE_BIT2 = 0,
  parameter integer SPARE_BIT3 = 0,
  parameter integer SPARE_BIT4 = 0,
  parameter integer SPARE_BIT5 = 0,
  parameter integer SPARE_BIT6 = 0,
  parameter integer SPARE_BIT7 = 0,
  parameter integer SPARE_BIT8 = 0,
  parameter [7:0] SPARE_BYTE0 = 8'h00,
  parameter [7:0] SPARE_BYTE1 = 8'h00,
  parameter [7:0] SPARE_BYTE2 = 8'h00,
  parameter [7:0] SPARE_BYTE3 = 8'h00,
  parameter [31:0] SPARE_WORD0 = 32'h00000000,
  parameter [31:0] SPARE_WORD1 = 32'h00000000,
  parameter [31:0] SPARE_WORD2 = 32'h00000000,
  parameter [31:0] SPARE_WORD3 = 32'h00000000,
  parameter SRIOV_CAP_ENABLE = "FALSE",
  parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hbebc20,
  parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2faf080,
  parameter [11:0] TL_CREDITS_CD = 12'h3e0,
  parameter [7:0] TL_CREDITS_CH = 8'h20,
  parameter [11:0] TL_CREDITS_NPD = 12'h028,
  parameter [7:0] TL_CREDITS_NPH = 8'h20,
  parameter [11:0] TL_CREDITS_PD = 12'h198,
  parameter [7:0] TL_CREDITS_PH = 8'h20,
  parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE",
  parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
  parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
  parameter TL_LEGACY_MODE_ENABLE = "FALSE",
  parameter [1:0] TL_PF_ENABLE_REG = 2'h0,
  parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE",
  parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE",
  parameter TWO_LAYER_MODE_ENABLE = "FALSE",
  parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE",
  parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000,
  parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50,
  parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF0_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF0_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF0_PM_CAP_ID = 8'h01,
  parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3,
  parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF0_TPHR_CAP_ENABLE = "FALSE",
  parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF0_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF1_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF1_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF1_PM_CAP_ID = 8'h01,
  parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3,
  parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF1_TPHR_CAP_ENABLE = "FALSE",
  parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF1_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF2_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF2_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF2_PM_CAP_ID = 8'h01,
  parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3,
  parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF2_TPHR_CAP_ENABLE = "FALSE",
  parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF2_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF3_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF3_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF3_PM_CAP_ID = 8'h01,
  parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3,
  parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF3_TPHR_CAP_ENABLE = "FALSE",
  parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF3_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF4_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF4_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF4_PM_CAP_ID = 8'h01,
  parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3,
  parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF4_TPHR_CAP_ENABLE = "FALSE",
  parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF4_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF5_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF5_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF5_PM_CAP_ID = 8'h01,
  parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3,
  parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF5_TPHR_CAP_ENABLE = "FALSE",
  parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF5_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF6_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF6_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF6_PM_CAP_ID = 8'h01,
  parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3,
  parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF6_TPHR_CAP_ENABLE = "FALSE",
  parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF6_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF7_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF7_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF7_PM_CAP_ID = 8'h01,
  parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3,
  parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF7_TPHR_CAP_ENABLE = "FALSE",
  parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF7_TPHR_CAP_VER = 4'h1
  ) (
  input  wire         core_clk,
  input  wire         user_clk,
  input  wire         pipe_clk,
  input  wire         phy_rdy,
  input  wire [C_DATA_WIDTH-1:0] s_axis_rq_tdata,
  input  wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep,
  input  wire         s_axis_rq_tlast,
  output wire   [3:0] s_axis_rq_tready,
  input  wire  [59:0] s_axis_rq_tuser,
  input  wire         s_axis_rq_tvalid,
  output wire [C_DATA_WIDTH-1:0] m_axis_rc_tdata,
  output wire [KEEP_WIDTH-1:0] m_axis_rc_tkeep,
  output wire         m_axis_rc_tlast,
  input  wire  [21:0] m_axis_rc_tready,
  output wire  [74:0] m_axis_rc_tuser,
  output wire         m_axis_rc_tvalid,
  output wire [C_DATA_WIDTH-1:0] m_axis_cq_tdata,
  output wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep,
  output wire         m_axis_cq_tlast,
  input  wire  [21:0] m_axis_cq_tready,
  output wire  [84:0] m_axis_cq_tuser,
  output wire         m_axis_cq_tvalid,
  input  wire [C_DATA_WIDTH-1:0] s_axis_cc_tdata,
  input  wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep,
  input  wire         s_axis_cc_tlast,
  output wire   [3:0] s_axis_cc_tready,
  input  wire  [32:0] s_axis_cc_tuser,
  input  wire         s_axis_cc_tvalid,
  output wire   [3:0] pcie_rq_seq_num,
  output wire         pcie_rq_seq_num_vld,
  output wire   [5:0] pcie_rq_tag,
  output wire   [1:0] pcie_rq_tag_av,
  output wire         pcie_rq_tag_vld,
  output wire   [1:0] pcie_tfc_npd_av,
  output wire   [1:0] pcie_tfc_nph_av,
  input  wire         pcie_cq_np_req,
  output wire   [5:0] pcie_cq_np_req_count,
  input  wire  [18:0] cfg_mgmt_addr,
  input  wire   [3:0] cfg_mgmt_byte_enable,
  input  wire         cfg_mgmt_read,
  output wire  [31:0] cfg_mgmt_read_data,
  output wire         cfg_mgmt_read_write_done,
  input  wire         cfg_mgmt_type1_cfg_reg_access,
  input  wire         cfg_mgmt_write,
  input  wire  [31:0] cfg_mgmt_write_data,
  output wire         cfg_phy_link_down,
  output wire   [1:0] cfg_phy_link_status,
  output wire   [3:0] cfg_negotiated_width,
  output wire   [2:0] cfg_current_speed,
  output wire   [2:0] cfg_max_payload,
  output wire   [2:0] cfg_max_read_req,
  output wire  [15:0] cfg_function_status,
  output wire  [11:0] cfg_function_power_state,
  output wire  [15:0] cfg_vf_status,
  output wire  [23:0] cfg_vf_power_state,
  output wire   [1:0] cfg_link_power_state,
  output wire         cfg_err_cor_out,
  output wire         cfg_err_nonfatal_out,
  output wire         cfg_err_fatal_out,
  output wire         cfg_local_error,
  output wire         cfg_ltr_enable,
  output wire   [5:0] cfg_ltssm_state,
  output wire   [3:0] cfg_rcb_status,
  output wire   [3:0] cfg_dpa_substate_change,
  output wire   [1:0] cfg_obff_enable,
  output wire         cfg_pl_status_change,
  output wire   [3:0] cfg_tph_requester_enable,
  output wire  [11:0] cfg_tph_st_mode,
  output wire   [7:0] cfg_vf_tph_requester_enable,
  output wire  [23:0] cfg_vf_tph_st_mode,
  output wire         cfg_msg_received,
  output wire   [7:0] cfg_msg_received_data,
  output wire   [4:0] cfg_msg_received_type,
  input  wire         cfg_msg_transmit,
  input  wire   [2:0] cfg_msg_transmit_type,
  input  wire  [31:0] cfg_msg_transmit_data,
  output wire         cfg_msg_transmit_done,
  output wire   [7:0] cfg_fc_ph,
  output wire  [11:0] cfg_fc_pd,
  output wire   [7:0] cfg_fc_nph,
  output wire  [11:0] cfg_fc_npd,
  output wire   [7:0] cfg_fc_cplh,
  output wire  [11:0] cfg_fc_cpld,
  input  wire   [2:0] cfg_fc_sel,
  input  wire   [2:0] cfg_per_func_status_control,
  output wire  [15:0] cfg_per_func_status_data,
  input  wire   [3:0] cfg_per_function_number,
  input  wire         cfg_per_function_output_request,
  output wire         cfg_per_function_update_done,
  input  wire         cfg_power_state_change_ack,
  output wire         cfg_power_state_change_interrupt,
  input  wire         cfg_err_cor_in,
  input  wire         cfg_err_uncor_in,
  output wire   [3:0] cfg_flr_in_process,
  input  wire   [3:0] cfg_flr_done,
  output wire   [7:0] cfg_vf_flr_in_process,
  input  wire   [7:0] cfg_vf_flr_done,
  input  wire         cfg_link_training_enable,
  input  wire   [3:0] cfg_interrupt_int,
  input  wire   [3:0] cfg_interrupt_pending,
  output wire         cfg_interrupt_sent,
  output wire   [3:0] cfg_interrupt_msi_enable,
  output wire   [7:0] cfg_interrupt_msi_vf_enable,
  output wire  [11:0] cfg_interrupt_msi_mmenable,
  output wire         cfg_interrupt_msi_mask_update,
  output wire  [31:0] cfg_interrupt_msi_data,
  input  wire   [3:0] cfg_interrupt_msi_select,
  input  wire  [31:0] cfg_interrupt_msi_int,
  input  wire  [31:0] cfg_interrupt_msi_pending_status,
  input  wire         cfg_interrupt_msi_pending_status_data_enable,
  input  wire   [3:0] cfg_interrupt_msi_pending_status_function_num,
  output wire         cfg_interrupt_msi_sent,
  output wire         cfg_interrupt_msi_fail,
  output wire   [3:0] cfg_interrupt_msix_enable,
  output wire   [3:0] cfg_interrupt_msix_mask,
  output wire   [7:0] cfg_interrupt_msix_vf_enable,
  output wire   [7:0] cfg_interrupt_msix_vf_mask,
  input  wire  [31:0] cfg_interrupt_msix_data,
  input  wire  [63:0] cfg_interrupt_msix_address,
  input  wire         cfg_interrupt_msix_int,
  output wire         cfg_interrupt_msix_sent,
  output wire         cfg_interrupt_msix_fail,
  input  wire   [2:0] cfg_interrupt_msi_attr,
  input  wire         cfg_interrupt_msi_tph_present,
  input  wire   [1:0] cfg_interrupt_msi_tph_type,
  input  wire   [8:0] cfg_interrupt_msi_tph_st_tag,
  input  wire   [3:0] cfg_interrupt_msi_function_number,
  output wire         cfg_ext_read_received,
  output wire         cfg_ext_write_received,
  output wire   [9:0] cfg_ext_register_number,
  output wire   [7:0] cfg_ext_function_number,
  output wire  [31:0] cfg_ext_write_data,
  output wire   [3:0] cfg_ext_write_byte_enable,
  input  wire  [31:0] cfg_ext_read_data,
  input  wire         cfg_ext_read_data_valid,
  input  wire  [15:0] cfg_dev_id,
  input  wire  [15:0] cfg_vend_id,
  input  wire   [7:0] cfg_rev_id,
  input  wire  [15:0] cfg_subsys_id,
  input  wire  [15:0] cfg_subsys_vend_id,
  input  wire   [7:0] cfg_ds_port_number,
  output wire         cfg_hot_reset_out,
  input  wire         cfg_config_space_enable,
  input  wire         cfg_req_pm_transition_l23_ready,
  input  wire         cfg_hot_reset_in,
  input  wire   [7:0] cfg_ds_bus_number,
  input  wire   [4:0] cfg_ds_device_number,
  input  wire   [2:0] cfg_ds_function_number,
  input  wire  [63:0] cfg_dsn,
  output wire         drp_rdy,
  output wire  [15:0] drp_do,
  input  wire         drp_clk,
  input  wire         drp_en,
  input  wire         drp_we,
  input  wire   [9:0] drp_addr,
  input  wire  [15:0] drp_di,
  input  wire   [4:0] user_tph_stt_address,
  input  wire   [3:0] user_tph_function_num,
  output wire  [31:0] user_tph_stt_read_data,
  output wire         user_tph_stt_read_data_valid,
  input  wire         user_tph_stt_read_enable,
  input  wire   [1:0] conf_req_type,
  input  wire   [3:0] conf_req_reg_num,
  input  wire  [31:0] conf_req_data,
  input  wire         conf_req_valid,
  input  wire         conf_mcap_request_by_conf,
  output wire         conf_req_ready,
  output wire  [31:0] conf_resp_rdata,
  output wire         conf_resp_valid,
  output wire         conf_mcap_design_switch,
  output wire         conf_mcap_eos,
  output wire         conf_mcap_in_use_by_pcie,
  output wire         dbg_mcap_cs_b,
  output wire  [31:0] dbg_mcap_data,
  output wire         dbg_mcap_eos,
  output wire         dbg_mcap_errror,
  output wire         dbg_mcap_mode,
  output wire         dbg_mcap_rdata_valid,
  output wire         dbg_mcap_rdwr_b,
  output wire         dbg_mcap_reset,
  input  wire         mcap_clk,
  output wire         mgmt_reset_n,
  output wire         pl_eq_in_progress,
  output wire   [1:0] pl_eq_phase,
  input  wire         pcie_perstn0_in,
  output wire         pcie_perstn0_out,
  input  wire         pcie_perstn1_in,
  output wire         pcie_perstn1_out,
  input  wire         pl_eq_reset_eieos_count,
  input  wire         pl_gen2_upstream_prefer_deemph,
  output wire         pipe_tx0_deemph_gt,
  output wire         pipe_tx0_rcvr_det_gt,
  output wire   [1:0] pipe_tx0_rate_gt,
  output wire   [2:0] pipe_tx0_margin_gt,
  output wire         pipe_tx0_swing_gt,
  input  wire   [5:0] pipe_tx_eqfs_gt,
  input  wire   [5:0] pipe_tx_eqlf_gt,
  output wire         pipe_tx0_reset_gt,
  output wire         pipe_tx0_compliance_gt,
  output wire         pipe_tx1_compliance_gt,
  output wire         pipe_tx2_compliance_gt,
  output wire         pipe_tx3_compliance_gt,
  output wire         pipe_tx4_compliance_gt,
  output wire         pipe_tx5_compliance_gt,
  output wire         pipe_tx6_compliance_gt,
  output wire         pipe_tx7_compliance_gt,
  output wire         pipe_tx0_data_valid_gt,
  output wire         pipe_tx1_data_valid_gt,
  output wire         pipe_tx2_data_valid_gt,
  output wire         pipe_tx3_data_valid_gt,
  output wire         pipe_tx4_data_valid_gt,
  output wire         pipe_tx5_data_valid_gt,
  output wire         pipe_tx6_data_valid_gt,
  output wire         pipe_tx7_data_valid_gt,
  output wire         pipe_tx0_elec_idle_gt,
  output wire         pipe_tx1_elec_idle_gt,
  output wire         pipe_tx2_elec_idle_gt,
  output wire         pipe_tx3_elec_idle_gt,
  output wire         pipe_tx4_elec_idle_gt,
  output wire         pipe_tx5_elec_idle_gt,
  output wire         pipe_tx6_elec_idle_gt,
  output wire         pipe_tx7_elec_idle_gt,
  output wire         pipe_tx0_start_block_gt,
  output wire         pipe_tx1_start_block_gt,
  output wire         pipe_tx2_start_block_gt,
  output wire         pipe_tx3_start_block_gt,
  output wire         pipe_tx4_start_block_gt,
  output wire         pipe_tx5_start_block_gt,
  output wire         pipe_tx6_start_block_gt,
  output wire         pipe_tx7_start_block_gt,
  output wire         pipe_rx0_polarity_gt,
  output wire         pipe_rx1_polarity_gt,
  output wire         pipe_rx2_polarity_gt,
  output wire         pipe_rx3_polarity_gt,
  output wire         pipe_rx4_polarity_gt,
  output wire         pipe_rx5_polarity_gt,
  output wire         pipe_rx6_polarity_gt,
  output wire         pipe_rx7_polarity_gt,
  output wire   [1:0] pipe_rx0_eqcontrol_gt,
  output wire   [1:0] pipe_rx1_eqcontrol_gt,
  output wire   [1:0] pipe_rx2_eqcontrol_gt,
  output wire   [1:0] pipe_rx3_eqcontrol_gt,
  output wire   [1:0] pipe_rx4_eqcontrol_gt,
  output wire   [1:0] pipe_rx5_eqcontrol_gt,
  output wire   [1:0] pipe_rx6_eqcontrol_gt,
  output wire   [1:0] pipe_rx7_eqcontrol_gt,
  output wire   [1:0] pipe_tx0_char_is_k_gt,
  output wire   [1:0] pipe_tx1_char_is_k_gt,
  output wire   [1:0] pipe_tx2_char_is_k_gt,
  output wire   [1:0] pipe_tx3_char_is_k_gt,
  output wire   [1:0] pipe_tx4_char_is_k_gt,
  output wire   [1:0] pipe_tx5_char_is_k_gt,
  output wire   [1:0] pipe_tx6_char_is_k_gt,
  output wire   [1:0] pipe_tx7_char_is_k_gt,
  output wire   [1:0] pipe_tx0_eqcontrol_gt,
  output wire   [1:0] pipe_tx1_eqcontrol_gt,
  output wire   [1:0] pipe_tx2_eqcontrol_gt,
  output wire   [1:0] pipe_tx3_eqcontrol_gt,
  output wire   [1:0] pipe_tx4_eqcontrol_gt,
  output wire   [1:0] pipe_tx5_eqcontrol_gt,
  output wire   [1:0] pipe_tx6_eqcontrol_gt,
  output wire   [1:0] pipe_tx7_eqcontrol_gt,
  output wire   [1:0] pipe_tx0_powerdown_gt,
  output wire   [1:0] pipe_tx1_powerdown_gt,
  output wire   [1:0] pipe_tx2_powerdown_gt,
  output wire   [1:0] pipe_tx3_powerdown_gt,
  output wire   [1:0] pipe_tx4_powerdown_gt,
  output wire   [1:0] pipe_tx5_powerdown_gt,
  output wire   [1:0] pipe_tx6_powerdown_gt,
  output wire   [1:0] pipe_tx7_powerdown_gt,
  output wire   [1:0] pipe_tx0_syncheader_gt,
  output wire   [1:0] pipe_tx1_syncheader_gt,
  output wire   [1:0] pipe_tx2_syncheader_gt,
  output wire   [1:0] pipe_tx3_syncheader_gt,
  output wire   [1:0] pipe_tx4_syncheader_gt,
  output wire   [1:0] pipe_tx5_syncheader_gt,
  output wire   [1:0] pipe_tx6_syncheader_gt,
  output wire   [1:0] pipe_tx7_syncheader_gt,
  output wire   [2:0] pipe_rx0_eqpreset_gt,
  output wire   [2:0] pipe_rx1_eqpreset_gt,
  output wire   [2:0] pipe_rx2_eqpreset_gt,
  output wire   [2:0] pipe_rx3_eqpreset_gt,
  output wire   [2:0] pipe_rx4_eqpreset_gt,
  output wire   [2:0] pipe_rx5_eqpreset_gt,
  output wire   [2:0] pipe_rx6_eqpreset_gt,
  output wire   [2:0] pipe_rx7_eqpreset_gt,
  output wire  [31:0] pipe_tx0_data_gt,
  output wire  [31:0] pipe_tx1_data_gt,
  output wire  [31:0] pipe_tx2_data_gt,
  output wire  [31:0] pipe_tx3_data_gt,
  output wire  [31:0] pipe_tx4_data_gt,
  output wire  [31:0] pipe_tx5_data_gt,
  output wire  [31:0] pipe_tx6_data_gt,
  output wire  [31:0] pipe_tx7_data_gt,
  output wire   [3:0] pipe_rx0_eqlp_txpreset_gt,
  output wire   [3:0] pipe_rx1_eqlp_txpreset_gt,
  output wire   [3:0] pipe_rx2_eqlp_txpreset_gt,
  output wire   [3:0] pipe_rx3_eqlp_txpreset_gt,
  output wire   [3:0] pipe_rx4_eqlp_txpreset_gt,
  output wire   [3:0] pipe_rx5_eqlp_txpreset_gt,
  output wire   [3:0] pipe_rx6_eqlp_txpreset_gt,
  output wire   [3:0] pipe_rx7_eqlp_txpreset_gt,
  output wire   [3:0] pipe_tx0_eqpreset_gt,
  output wire   [3:0] pipe_tx1_eqpreset_gt,
  output wire   [3:0] pipe_tx2_eqpreset_gt,
  output wire   [3:0] pipe_tx3_eqpreset_gt,
  output wire   [3:0] pipe_tx4_eqpreset_gt,
  output wire   [3:0] pipe_tx5_eqpreset_gt,
  output wire   [3:0] pipe_tx6_eqpreset_gt,
  output wire   [3:0] pipe_tx7_eqpreset_gt,
  output wire   [5:0] pipe_rx0_eqlp_lffs_gt,
  output wire   [5:0] pipe_rx1_eqlp_lffs_gt,
  output wire   [5:0] pipe_rx2_eqlp_lffs_gt,
  output wire   [5:0] pipe_rx3_eqlp_lffs_gt,
  output wire   [5:0] pipe_rx4_eqlp_lffs_gt,
  output wire   [5:0] pipe_rx5_eqlp_lffs_gt,
  output wire   [5:0] pipe_rx6_eqlp_lffs_gt,
  output wire   [5:0] pipe_rx7_eqlp_lffs_gt,
  output wire   [5:0] pipe_tx0_eqdeemph_gt,
  output wire   [5:0] pipe_tx1_eqdeemph_gt,
  output wire   [5:0] pipe_tx2_eqdeemph_gt,
  output wire   [5:0] pipe_tx3_eqdeemph_gt,
  output wire   [5:0] pipe_tx4_eqdeemph_gt,
  output wire   [5:0] pipe_tx5_eqdeemph_gt,
  output wire   [5:0] pipe_tx6_eqdeemph_gt,
  output wire   [5:0] pipe_tx7_eqdeemph_gt,
  input  wire         pipe_rx0_data_valid_gt,
  input  wire         pipe_rx1_data_valid_gt,
  input  wire         pipe_rx2_data_valid_gt,
  input  wire         pipe_rx3_data_valid_gt,
  input  wire         pipe_rx4_data_valid_gt,
  input  wire         pipe_rx5_data_valid_gt,
  input  wire         pipe_rx6_data_valid_gt,
  input  wire         pipe_rx7_data_valid_gt,
  input  wire         pipe_rx0_elec_idle_gt,
  input  wire         pipe_rx1_elec_idle_gt,
  input  wire         pipe_rx2_elec_idle_gt,
  input  wire         pipe_rx3_elec_idle_gt,
  input  wire         pipe_rx4_elec_idle_gt,
  input  wire         pipe_rx5_elec_idle_gt,
  input  wire         pipe_rx6_elec_idle_gt,
  input  wire         pipe_rx7_elec_idle_gt,
  input  wire         pipe_rx0_eqdone_gt,
  input  wire         pipe_rx1_eqdone_gt,
  input  wire         pipe_rx2_eqdone_gt,
  input  wire         pipe_rx3_eqdone_gt,
  input  wire         pipe_rx4_eqdone_gt,
  input  wire         pipe_rx5_eqdone_gt,
  input  wire         pipe_rx6_eqdone_gt,
  input  wire         pipe_rx7_eqdone_gt,
  input  wire         pipe_rx0_eqlp_adaptdone_gt,
  input  wire         pipe_rx1_eqlp_adaptdone_gt,
  input  wire         pipe_rx2_eqlp_adaptdone_gt,
  input  wire         pipe_rx3_eqlp_adaptdone_gt,
  input  wire         pipe_rx4_eqlp_adaptdone_gt,
  input  wire         pipe_rx5_eqlp_adaptdone_gt,
  input  wire         pipe_rx6_eqlp_adaptdone_gt,
  input  wire         pipe_rx7_eqlp_adaptdone_gt,
  input  wire         pipe_rx0_eqlp_lffs_sel_gt,
  input  wire         pipe_rx1_eqlp_lffs_sel_gt,
  input  wire         pipe_rx2_eqlp_lffs_sel_gt,
  input  wire         pipe_rx3_eqlp_lffs_sel_gt,
  input  wire         pipe_rx4_eqlp_lffs_sel_gt,
  input  wire         pipe_rx5_eqlp_lffs_sel_gt,
  input  wire         pipe_rx6_eqlp_lffs_sel_gt,
  input  wire         pipe_rx7_eqlp_lffs_sel_gt,
  input  wire         pipe_rx0_phy_status_gt,
  input  wire         pipe_rx1_phy_status_gt,
  input  wire         pipe_rx2_phy_status_gt,
  input  wire         pipe_rx3_phy_status_gt,
  input  wire         pipe_rx4_phy_status_gt,
  input  wire         pipe_rx5_phy_status_gt,
  input  wire         pipe_rx6_phy_status_gt,
  input  wire         pipe_rx7_phy_status_gt,
  input  wire         pipe_rx0_start_block_gt,
  input  wire         pipe_rx1_start_block_gt,
  input  wire         pipe_rx2_start_block_gt,
  input  wire         pipe_rx3_start_block_gt,
  input  wire         pipe_rx4_start_block_gt,
  input  wire         pipe_rx5_start_block_gt,
  input  wire         pipe_rx6_start_block_gt,
  input  wire         pipe_rx7_start_block_gt,
  input  wire         pipe_rx0_valid_gt,
  input  wire         pipe_rx1_valid_gt,
  input  wire         pipe_rx2_valid_gt,
  input  wire         pipe_rx3_valid_gt,
  input  wire         pipe_rx4_valid_gt,
  input  wire         pipe_rx5_valid_gt,
  input  wire         pipe_rx6_valid_gt,
  input  wire         pipe_rx7_valid_gt,
  input  wire         pipe_tx0_eqdone_gt,
  input  wire         pipe_tx1_eqdone_gt,
  input  wire         pipe_tx2_eqdone_gt,
  input  wire         pipe_tx3_eqdone_gt,
  input  wire         pipe_tx4_eqdone_gt,
  input  wire         pipe_tx5_eqdone_gt,
  input  wire         pipe_tx6_eqdone_gt,
  input  wire         pipe_tx7_eqdone_gt,
  input  wire  [17:0] pipe_rx0_eqlp_new_txcoef_forpreset_gt,
  input  wire  [17:0] pipe_rx1_eqlp_new_txcoef_forpreset_gt,
  input  wire  [17:0] pipe_rx2_eqlp_new_txcoef_forpreset_gt,
  input  wire  [17:0] pipe_rx3_eqlp_new_txcoef_forpreset_gt,
  input  wire  [17:0] pipe_rx4_eqlp_new_txcoef_forpreset_gt,
  input  wire  [17:0] pipe_rx5_eqlp_new_txcoef_forpreset_gt,
  input  wire  [17:0] pipe_rx6_eqlp_new_txcoef_forpreset_gt,
  input  wire  [17:0] pipe_rx7_eqlp_new_txcoef_forpreset_gt,
  input  wire  [17:0] pipe_tx0_eqcoeff_gt,
  input  wire  [17:0] pipe_tx1_eqcoeff_gt,
  input  wire  [17:0] pipe_tx2_eqcoeff_gt,
  input  wire  [17:0] pipe_tx3_eqcoeff_gt,
  input  wire  [17:0] pipe_tx4_eqcoeff_gt,
  input  wire  [17:0] pipe_tx5_eqcoeff_gt,
  input  wire  [17:0] pipe_tx6_eqcoeff_gt,
  input  wire  [17:0] pipe_tx7_eqcoeff_gt,
  input  wire   [1:0] pipe_rx0_char_is_k_gt,
  input  wire   [1:0] pipe_rx1_char_is_k_gt,
  input  wire   [1:0] pipe_rx2_char_is_k_gt,
  input  wire   [1:0] pipe_rx3_char_is_k_gt,
  input  wire   [1:0] pipe_rx4_char_is_k_gt,
  input  wire   [1:0] pipe_rx5_char_is_k_gt,
  input  wire   [1:0] pipe_rx6_char_is_k_gt,
  input  wire   [1:0] pipe_rx7_char_is_k_gt,
  input  wire   [1:0] pipe_rx0_syncheader_gt,
  input  wire   [1:0] pipe_rx1_syncheader_gt,
  input  wire   [1:0] pipe_rx2_syncheader_gt,
  input  wire   [1:0] pipe_rx3_syncheader_gt,
  input  wire   [1:0] pipe_rx4_syncheader_gt,
  input  wire   [1:0] pipe_rx5_syncheader_gt,
  input  wire   [1:0] pipe_rx6_syncheader_gt,
  input  wire   [1:0] pipe_rx7_syncheader_gt,
  input  wire   [2:0] pipe_rx0_status_gt,
  input  wire   [2:0] pipe_rx1_status_gt,
  input  wire   [2:0] pipe_rx2_status_gt,
  input  wire   [2:0] pipe_rx3_status_gt,
  input  wire   [2:0] pipe_rx4_status_gt,
  input  wire   [2:0] pipe_rx5_status_gt,
  input  wire   [2:0] pipe_rx6_status_gt,
  input  wire   [2:0] pipe_rx7_status_gt,
  input  wire  [31:0] pipe_rx0_data_gt,
  input  wire  [31:0] pipe_rx1_data_gt,
  input  wire  [31:0] pipe_rx2_data_gt,
  input  wire  [31:0] pipe_rx3_data_gt,
  input  wire  [31:0] pipe_rx4_data_gt,
  input  wire  [31:0] pipe_rx5_data_gt,
  input  wire  [31:0] pipe_rx6_data_gt,
  input  wire  [31:0] pipe_rx7_data_gt
  );

  wire                pipe_tx0_rcvr_det;
  wire                pipe_tx0_reset;
  wire          [1:0] pipe_tx0_rate;
  wire                pipe_tx0_deemph;
  wire          [2:0] pipe_tx0_margin;
  wire                pipe_tx0_swing;
  wire          [5:0] pipe_tx_eqfs;
  wire          [5:0] pipe_tx_eqlf;
  wire          [1:0] pipe_rx0_char_is_k;
  wire         [31:0] pipe_rx0_data;
  wire                pipe_rx0_valid;
  wire                pipe_rx0_data_valid;
  wire          [2:0] pipe_rx0_status;
  wire                pipe_rx0_phy_status;
  wire                pipe_rx0_elec_idle;
  wire                pipe_rx0_eqdone;
  wire                pipe_rx0_eqlp_adaptdone;
  wire                pipe_rx0_eqlp_lffs_sel;
  wire          [3:0] pipe_rx0_eqlp_txpreset;
  wire         [17:0] pipe_rx0_eqlp_new_txcoef_forpreset;
  wire                pipe_rx0_start_block;
  wire          [1:0] pipe_rx0_syncheader;
  wire                pipe_rx0_polarity;
  wire          [1:0] pipe_rx0_eqcontrol;
  wire          [5:0] pipe_rx0_eqlp_lffs;
  wire          [2:0] pipe_rx0_eqpreset;
  wire         [17:0] pipe_tx0_eqcoeff;
  wire                pipe_tx0_eqdone;
  wire                pipe_tx0_compliance;
  wire          [1:0] pipe_tx0_char_is_k;
  wire         [31:0] pipe_tx0_data;
  wire                pipe_tx0_elec_idle;
  wire          [1:0] pipe_tx0_powerdown;
  wire                pipe_tx0_data_valid;
  wire                pipe_tx0_start_block;
  wire          [1:0] pipe_tx0_syncheader;
  wire          [1:0] pipe_tx0_eqcontrol;
  wire          [5:0] pipe_tx0_eqdeemph;
  wire          [3:0] pipe_tx0_eqpreset;
  wire          [1:0] pipe_rx1_char_is_k;
  wire         [31:0] pipe_rx1_data;
  wire                pipe_rx1_valid;
  wire                pipe_rx1_data_valid;
  wire          [2:0] pipe_rx1_status;
  wire                pipe_rx1_phy_status;
  wire                pipe_rx1_elec_idle;
  wire                pipe_rx1_eqdone;
  wire                pipe_rx1_eqlp_adaptdone;
  wire                pipe_rx1_eqlp_lffs_sel;
  wire          [3:0] pipe_rx1_eqlp_txpreset;
  wire         [17:0] pipe_rx1_eqlp_new_txcoef_forpreset;
  wire                pipe_rx1_start_block;
  wire          [1:0] pipe_rx1_syncheader;
  wire                pipe_rx1_polarity;
  wire          [1:0] pipe_rx1_eqcontrol;
  wire          [5:0] pipe_rx1_eqlp_lffs;
  wire          [2:0] pipe_rx1_eqpreset;
  wire         [17:0] pipe_tx1_eqcoeff;
  wire                pipe_tx1_eqdone;
  wire                pipe_tx1_compliance;
  wire          [1:0] pipe_tx1_char_is_k;
  wire         [31:0] pipe_tx1_data;
  wire                pipe_tx1_elec_idle;
  wire          [1:0] pipe_tx1_powerdown;
  wire                pipe_tx1_data_valid;
  wire                pipe_tx1_start_block;
  wire          [1:0] pipe_tx1_syncheader;
  wire          [1:0] pipe_tx1_eqcontrol;
  wire          [5:0] pipe_tx1_eqdeemph;
  wire          [3:0] pipe_tx1_eqpreset;
  wire          [1:0] pipe_rx2_char_is_k;
  wire         [31:0] pipe_rx2_data;
  wire                pipe_rx2_valid;
  wire                pipe_rx2_data_valid;
  wire          [2:0] pipe_rx2_status;
  wire                pipe_rx2_phy_status;
  wire                pipe_rx2_elec_idle;
  wire                pipe_rx2_eqdone;
  wire                pipe_rx2_eqlp_adaptdone;
  wire                pipe_rx2_eqlp_lffs_sel;
  wire          [3:0] pipe_rx2_eqlp_txpreset;
  wire         [17:0] pipe_rx2_eqlp_new_txcoef_forpreset;
  wire                pipe_rx2_start_block;
  wire          [1:0] pipe_rx2_syncheader;
  wire                pipe_rx2_polarity;
  wire          [1:0] pipe_rx2_eqcontrol;
  wire          [5:0] pipe_rx2_eqlp_lffs;
  wire          [2:0] pipe_rx2_eqpreset;
  wire         [17:0] pipe_tx2_eqcoeff;
  wire                pipe_tx2_eqdone;
  wire                pipe_tx2_compliance;
  wire          [1:0] pipe_tx2_char_is_k;
  wire         [31:0] pipe_tx2_data;
  wire                pipe_tx2_elec_idle;
  wire          [1:0] pipe_tx2_powerdown;
  wire                pipe_tx2_data_valid;
  wire                pipe_tx2_start_block;
  wire          [1:0] pipe_tx2_syncheader;
  wire          [1:0] pipe_tx2_eqcontrol;
  wire          [5:0] pipe_tx2_eqdeemph;
  wire          [3:0] pipe_tx2_eqpreset;
  wire          [1:0] pipe_rx3_char_is_k;
  wire         [31:0] pipe_rx3_data;
  wire                pipe_rx3_valid;
  wire                pipe_rx3_data_valid;
  wire          [2:0] pipe_rx3_status;
  wire                pipe_rx3_phy_status;
  wire                pipe_rx3_elec_idle;
  wire                pipe_rx3_eqdone;
  wire                pipe_rx3_eqlp_adaptdone;
  wire                pipe_rx3_eqlp_lffs_sel;
  wire          [3:0] pipe_rx3_eqlp_txpreset;
  wire         [17:0] pipe_rx3_eqlp_new_txcoef_forpreset;
  wire                pipe_rx3_start_block;
  wire          [1:0] pipe_rx3_syncheader;
  wire                pipe_rx3_polarity;
  wire          [1:0] pipe_rx3_eqcontrol;
  wire          [5:0] pipe_rx3_eqlp_lffs;
  wire          [2:0] pipe_rx3_eqpreset;
  wire         [17:0] pipe_tx3_eqcoeff;
  wire                pipe_tx3_eqdone;
  wire                pipe_tx3_compliance;
  wire          [1:0] pipe_tx3_char_is_k;
  wire         [31:0] pipe_tx3_data;
  wire                pipe_tx3_elec_idle;
  wire          [1:0] pipe_tx3_powerdown;
  wire                pipe_tx3_data_valid;
  wire                pipe_tx3_start_block;
  wire          [1:0] pipe_tx3_syncheader;
  wire          [1:0] pipe_tx3_eqcontrol;
  wire          [5:0] pipe_tx3_eqdeemph;
  wire          [3:0] pipe_tx3_eqpreset;
  wire          [1:0] pipe_rx4_char_is_k;
  wire         [31:0] pipe_rx4_data;
  wire                pipe_rx4_valid;
  wire                pipe_rx4_data_valid;
  wire          [2:0] pipe_rx4_status;
  wire                pipe_rx4_phy_status;
  wire                pipe_rx4_elec_idle;
  wire                pipe_rx4_eqdone;
  wire                pipe_rx4_eqlp_adaptdone;
  wire                pipe_rx4_eqlp_lffs_sel;
  wire          [3:0] pipe_rx4_eqlp_txpreset;
  wire         [17:0] pipe_rx4_eqlp_new_txcoef_forpreset;
  wire                pipe_rx4_start_block;
  wire          [1:0] pipe_rx4_syncheader;
  wire                pipe_rx4_polarity;
  wire          [1:0] pipe_rx4_eqcontrol;
  wire          [5:0] pipe_rx4_eqlp_lffs;
  wire          [2:0] pipe_rx4_eqpreset;
  wire         [17:0] pipe_tx4_eqcoeff;
  wire                pipe_tx4_eqdone;
  wire                pipe_tx4_compliance;
  wire          [1:0] pipe_tx4_char_is_k;
  wire         [31:0] pipe_tx4_data;
  wire                pipe_tx4_elec_idle;
  wire          [1:0] pipe_tx4_powerdown;
  wire                pipe_tx4_data_valid;
  wire                pipe_tx4_start_block;
  wire          [1:0] pipe_tx4_syncheader;
  wire          [1:0] pipe_tx4_eqcontrol;
  wire          [5:0] pipe_tx4_eqdeemph;
  wire          [3:0] pipe_tx4_eqpreset;
  wire          [1:0] pipe_rx5_char_is_k;
  wire         [31:0] pipe_rx5_data;
  wire                pipe_rx5_valid;
  wire                pipe_rx5_data_valid;
  wire          [2:0] pipe_rx5_status;
  wire                pipe_rx5_phy_status;
  wire                pipe_rx5_elec_idle;
  wire                pipe_rx5_eqdone;
  wire                pipe_rx5_eqlp_adaptdone;
  wire                pipe_rx5_eqlp_lffs_sel;
  wire          [3:0] pipe_rx5_eqlp_txpreset;
  wire         [17:0] pipe_rx5_eqlp_new_txcoef_forpreset;
  wire                pipe_rx5_start_block;
  wire          [1:0] pipe_rx5_syncheader;
  wire                pipe_rx5_polarity;
  wire          [1:0] pipe_rx5_eqcontrol;
  wire          [5:0] pipe_rx5_eqlp_lffs;
  wire          [2:0] pipe_rx5_eqpreset;
  wire         [17:0] pipe_tx5_eqcoeff;
  wire                pipe_tx5_eqdone;
  wire                pipe_tx5_compliance;
  wire          [1:0] pipe_tx5_char_is_k;
  wire         [31:0] pipe_tx5_data;
  wire                pipe_tx5_elec_idle;
  wire          [1:0] pipe_tx5_powerdown;
  wire                pipe_tx5_data_valid;
  wire                pipe_tx5_start_block;
  wire          [1:0] pipe_tx5_syncheader;
  wire          [1:0] pipe_tx5_eqcontrol;
  wire          [5:0] pipe_tx5_eqdeemph;
  wire          [3:0] pipe_tx5_eqpreset;
  wire          [1:0] pipe_rx6_char_is_k;
  wire         [31:0] pipe_rx6_data;
  wire                pipe_rx6_valid;
  wire                pipe_rx6_data_valid;
  wire          [2:0] pipe_rx6_status;
  wire                pipe_rx6_phy_status;
  wire                pipe_rx6_elec_idle;
  wire                pipe_rx6_eqdone;
  wire                pipe_rx6_eqlp_adaptdone;
  wire                pipe_rx6_eqlp_lffs_sel;
  wire          [3:0] pipe_rx6_eqlp_txpreset;
  wire         [17:0] pipe_rx6_eqlp_new_txcoef_forpreset;
  wire                pipe_rx6_start_block;
  wire          [1:0] pipe_rx6_syncheader;
  wire                pipe_rx6_polarity;
  wire          [1:0] pipe_rx6_eqcontrol;
  wire          [5:0] pipe_rx6_eqlp_lffs;
  wire          [2:0] pipe_rx6_eqpreset;
  wire         [17:0] pipe_tx6_eqcoeff;
  wire                pipe_tx6_eqdone;
  wire                pipe_tx6_compliance;
  wire          [1:0] pipe_tx6_char_is_k;
  wire         [31:0] pipe_tx6_data;
  wire                pipe_tx6_elec_idle;
  wire          [1:0] pipe_tx6_powerdown;
  wire                pipe_tx6_data_valid;
  wire                pipe_tx6_start_block;
  wire          [1:0] pipe_tx6_syncheader;
  wire          [1:0] pipe_tx6_eqcontrol;
  wire          [5:0] pipe_tx6_eqdeemph;
  wire          [3:0] pipe_tx6_eqpreset;
  wire          [1:0] pipe_rx7_char_is_k;
  wire         [31:0] pipe_rx7_data;
  wire                pipe_rx7_valid;
  wire                pipe_rx7_data_valid;
  wire          [2:0] pipe_rx7_status;
  wire                pipe_rx7_phy_status;
  wire                pipe_rx7_elec_idle;
  wire                pipe_rx7_eqdone;
  wire                pipe_rx7_eqlp_adaptdone;
  wire                pipe_rx7_eqlp_lffs_sel;
  wire          [3:0] pipe_rx7_eqlp_txpreset;
  wire         [17:0] pipe_rx7_eqlp_new_txcoef_forpreset;
  wire                pipe_rx7_start_block;
  wire          [1:0] pipe_rx7_syncheader;
  wire                pipe_rx7_polarity;
  wire          [1:0] pipe_rx7_eqcontrol;
  wire          [5:0] pipe_rx7_eqlp_lffs;
  wire          [2:0] pipe_rx7_eqpreset;
  wire         [17:0] pipe_tx7_eqcoeff;
  wire                pipe_tx7_eqdone;
  wire                pipe_tx7_compliance;
  wire          [1:0] pipe_tx7_char_is_k;
  wire         [31:0] pipe_tx7_data;
  wire                pipe_tx7_elec_idle;
  wire          [1:0] pipe_tx7_powerdown;
  wire                pipe_tx7_data_valid;
  wire                pipe_tx7_start_block;
  wire          [1:0] pipe_tx7_syncheader;
  wire          [1:0] pipe_tx7_eqcontrol;
  wire          [5:0] pipe_tx7_eqdeemph;
  wire          [3:0] pipe_tx7_eqpreset;
  wire                reset_n;
  wire                pipe_reset_n;
  wire                mgmt_sticky_reset_n;
  wire          [4:0] cfg_tph_stt_address;
  wire          [3:0] cfg_tph_function_num;
  wire         [31:0] cfg_tph_stt_write_data;
  wire                cfg_tph_stt_write_enable;
  wire          [3:0] cfg_tph_stt_write_byte_valid;
  wire         [31:0] cfg_tph_stt_read_data;
  wire                cfg_tph_stt_read_enable;
  wire                cfg_tph_stt_read_data_valid;

  wire  [255:0] s_axis_cc_tdata_i; 
  wire  [255:0] s_axis_rq_tdata_i;
  wire  [255:0] m_axis_cq_tdata_i;
  wire  [255:0] m_axis_rc_tdata_i;
  wire  [7:0]   s_axis_cc_tkeep_i;
  wire  [7:0]   s_axis_rq_tkeep_i;
  wire  [7:0]   m_axis_cq_tkeep_i;
  wire  [7:0]   m_axis_rc_tkeep_i;

  generate
if (PL_UPSTREAM_FACING == "TRUE") begin : axis_mapping_ep
assign s_axis_cc_tdata_i = s_axis_cc_tdata; // I
assign s_axis_rq_tdata_i = s_axis_rq_tdata; // I
assign s_axis_cc_tkeep_i = s_axis_cc_tkeep; // I
assign s_axis_rq_tkeep_i = s_axis_rq_tkeep; // I
assign m_axis_cq_tdata = m_axis_cq_tdata_i; // O
assign m_axis_rc_tdata = m_axis_rc_tdata_i; // O
assign m_axis_cq_tkeep = m_axis_cq_tkeep_i; // O
assign m_axis_rc_tkeep = m_axis_rc_tkeep_i; // O
end // axis_mapping_ep
  endgenerate

  generate
if (PL_UPSTREAM_FACING == "FALSE") begin : axis_mapping_rp
assign s_axis_cc_tdata_i = s_axis_cc_tdata; // I
assign s_axis_rq_tdata_i = s_axis_rq_tdata; // I
assign s_axis_cc_tkeep_i = s_axis_cc_tkeep; // I
assign s_axis_rq_tkeep_i = s_axis_rq_tkeep; // I
assign m_axis_cq_tdata = m_axis_cq_tdata_i; // O
assign m_axis_rc_tdata = m_axis_rc_tdata_i; // O
assign m_axis_cq_tkeep = m_axis_cq_tkeep_i; // O
assign m_axis_rc_tkeep = m_axis_rc_tkeep_i; // O
end // axis_mapping_rp
  endgenerate

  xdma_x8gen3_pcie3_ip_init_ctrl #(
    .TCQ (TCQ),
    .PL_UPSTREAM_FACING(PL_UPSTREAM_FACING))
  init_ctrl_inst (
    .clk_i                 (user_clk),
    .reset_n_o             (reset_n),
    .pipe_reset_n_o        (pipe_reset_n),
    .mgmt_reset_n_o        (mgmt_reset_n),
    .mgmt_sticky_reset_n_o (mgmt_sticky_reset_n),
    .phy_rdy_i             (phy_rdy),
    .state_o               ()
  );

  xdma_x8gen3_pcie3_ip_tph_tbl #(
    .TCQ (TCQ))
  tph_tbl_inst (
    .user_clk (user_clk),
    .reset_n (reset_n),
    .cfg_tph_stt_address_i (cfg_tph_stt_address),
    .cfg_tph_function_num_i (cfg_tph_function_num),
    .cfg_tph_stt_write_data_i (cfg_tph_stt_write_data),
    .cfg_tph_stt_write_enable_i (cfg_tph_stt_write_enable),
    .cfg_tph_stt_write_byte_valid_i (cfg_tph_stt_write_byte_valid),
    .cfg_tph_stt_read_data_o (cfg_tph_stt_read_data),
    .cfg_tph_stt_read_enable_i (cfg_tph_stt_read_enable),
    .cfg_tph_stt_read_data_valid_o (cfg_tph_stt_read_data_valid),
    .user_tph_stt_address_i (user_tph_stt_address),
    .user_tph_function_num_i (user_tph_function_num),
    .user_tph_stt_read_data_o (user_tph_stt_read_data),
    .user_tph_stt_read_data_valid_o (user_tph_stt_read_data_valid),
    .user_tph_stt_read_enable_i (user_tph_stt_read_enable)
  );

  xdma_x8gen3_pcie3_ip_pipe_pipeline 
 #(
    .TCQ (TCQ),
    .PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH),
    .PIPE_PIPELINE_STAGES (PIPE_PIPELINE_STAGES))
  pipe_pipeline_inst (
    .rst_n                               (reset_n),
    .pipe_clk                            (pipe_clk),
    .pipe_tx_rcvr_det_i                  (pipe_tx0_rcvr_det),
    .pipe_tx_reset_i                     (pipe_tx0_reset),
    .pipe_tx_rate_i                      (pipe_tx0_rate),
    .pipe_tx_deemph_i                    (pipe_tx0_deemph),
    .pipe_tx_margin_i                    (pipe_tx0_margin),
    .pipe_tx_swing_i                     (pipe_tx0_swing),
    .pipe_tx_eqfs_i (pipe_tx_eqfs_gt),
    .pipe_tx_eqlf_i (pipe_tx_eqlf_gt),
    .pipe_tx_rcvr_det_o                  (pipe_tx0_rcvr_det_gt),
    .pipe_tx_reset_o                     (pipe_tx0_reset_gt),
    .pipe_tx_rate_o                      (pipe_tx0_rate_gt),
    .pipe_tx_deemph_o                    (pipe_tx0_deemph_gt),
    .pipe_tx_margin_o                    (pipe_tx0_margin_gt),
    .pipe_tx_swing_o                     (pipe_tx0_swing_gt),
    .pipe_tx_eqfs_o (pipe_tx_eqfs),
    .pipe_tx_eqlf_o (pipe_tx_eqlf),
    .pipe_rx0_char_is_k_o (pipe_rx0_char_is_k),
    .pipe_rx0_data_o (pipe_rx0_data),
    .pipe_rx0_valid_o (pipe_rx0_valid),
    .pipe_rx0_data_valid_o (pipe_rx0_data_valid),
    .pipe_rx0_status_o (pipe_rx0_status),
    .pipe_rx0_phy_status_o (pipe_rx0_phy_status),
    .pipe_rx0_elec_idle_o (pipe_rx0_elec_idle),
    .pipe_rx0_eqdone_o (pipe_rx0_eqdone),
    .pipe_rx0_eqlpadaptdone_o (pipe_rx0_eqlp_adaptdone),
    .pipe_rx0_eqlplffssel_o (pipe_rx0_eqlp_lffs_sel),
    .pipe_rx0_eqlpnewtxcoefforpreset_o (pipe_rx0_eqlp_new_txcoef_forpreset),
    .pipe_rx0_startblock_o (pipe_rx0_start_block),
    .pipe_rx0_syncheader_o (pipe_rx0_syncheader),
    .pipe_rx0_polarity_i (pipe_rx0_polarity),
    .pipe_rx0_eqcontrol_i (pipe_rx0_eqcontrol),
    .pipe_rx0_eqlplffs_i (pipe_rx0_eqlp_lffs),
    .pipe_rx0_eqlptxpreset_i (pipe_rx0_eqlp_txpreset),
    .pipe_rx0_eqpreset_i (pipe_rx0_eqpreset),
    .pipe_tx0_eqcoeff_o (pipe_tx0_eqcoeff),
    .pipe_tx0_eqdone_o (pipe_tx0_eqdone),
    .pipe_tx0_compliance_i (pipe_tx0_compliance),
    .pipe_tx0_char_is_k_i (pipe_tx0_char_is_k),
    .pipe_tx0_data_i (pipe_tx0_data),
    .pipe_tx0_elec_idle_i (pipe_tx0_elec_idle),
    .pipe_tx0_powerdown_i (pipe_tx0_powerdown),
    .pipe_tx0_datavalid_i (pipe_tx0_data_valid),
    .pipe_tx0_startblock_i (pipe_tx0_start_block),
    .pipe_tx0_syncheader_i (pipe_tx0_syncheader),
    .pipe_tx0_eqcontrol_i (pipe_tx0_eqcontrol),
    .pipe_tx0_eqdeemph_i (pipe_tx0_eqdeemph),
    .pipe_tx0_eqpreset_i (pipe_tx0_eqpreset),
    .pipe_rx0_char_is_k_i (pipe_rx0_char_is_k_gt),
    .pipe_rx0_data_i (pipe_rx0_data_gt),
    .pipe_rx0_valid_i (pipe_rx0_valid_gt),
    .pipe_rx0_data_valid_i (pipe_rx0_data_valid_gt),
    .pipe_rx0_status_i (pipe_rx0_status_gt),
    .pipe_rx0_phy_status_i (pipe_rx0_phy_status_gt),
    .pipe_rx0_elec_idle_i (pipe_rx0_elec_idle_gt),
    .pipe_rx0_eqdone_i (pipe_rx0_eqdone_gt),
    .pipe_rx0_eqlpadaptdone_i (pipe_rx0_eqlp_adaptdone_gt),
    .pipe_rx0_eqlplffssel_i (pipe_rx0_eqlp_lffs_sel_gt),
    .pipe_rx0_eqlpnewtxcoefforpreset_i (pipe_rx0_eqlp_new_txcoef_forpreset_gt),
    .pipe_rx0_startblock_i (pipe_rx0_start_block_gt),
    .pipe_rx0_syncheader_i (pipe_rx0_syncheader_gt),
    .pipe_rx0_polarity_o (pipe_rx0_polarity_gt),
    .pipe_rx0_eqcontrol_o (pipe_rx0_eqcontrol_gt),
    .pipe_rx0_eqlplffs_o (pipe_rx0_eqlp_lffs_gt),
    .pipe_rx0_eqlptxpreset_o (pipe_rx0_eqlp_txpreset_gt),
    .pipe_rx0_eqpreset_o (pipe_rx0_eqpreset_gt),
    .pipe_tx0_eqcoeff_i (pipe_tx0_eqcoeff_gt),
    .pipe_tx0_eqdone_i (pipe_tx0_eqdone_gt),
    .pipe_tx0_compliance_o (pipe_tx0_compliance_gt),
    .pipe_tx0_char_is_k_o (pipe_tx0_char_is_k_gt),
    .pipe_tx0_data_o (pipe_tx0_data_gt),
    .pipe_tx0_elec_idle_o (pipe_tx0_elec_idle_gt),
    .pipe_tx0_powerdown_o (pipe_tx0_powerdown_gt),
    .pipe_tx0_datavalid_o (pipe_tx0_data_valid_gt),
    .pipe_tx0_startblock_o (pipe_tx0_start_block_gt),
    .pipe_tx0_syncheader_o (pipe_tx0_syncheader_gt),
    .pipe_tx0_eqcontrol_o (pipe_tx0_eqcontrol_gt),
    .pipe_tx0_eqdeemph_o (pipe_tx0_eqdeemph_gt),
    .pipe_tx0_eqpreset_o (pipe_tx0_eqpreset_gt),
    .pipe_rx1_char_is_k_o (pipe_rx1_char_is_k),
    .pipe_rx1_data_o (pipe_rx1_data),
    .pipe_rx1_valid_o (pipe_rx1_valid),
    .pipe_rx1_data_valid_o (pipe_rx1_data_valid),
    .pipe_rx1_status_o (pipe_rx1_status),
    .pipe_rx1_phy_status_o (pipe_rx1_phy_status),
    .pipe_rx1_elec_idle_o (pipe_rx1_elec_idle),
    .pipe_rx1_eqdone_o (pipe_rx1_eqdone),
    .pipe_rx1_eqlpadaptdone_o (pipe_rx1_eqlp_adaptdone),
    .pipe_rx1_eqlplffssel_o (pipe_rx1_eqlp_lffs_sel),
    .pipe_rx1_eqlpnewtxcoefforpreset_o (pipe_rx1_eqlp_new_txcoef_forpreset),
    .pipe_rx1_startblock_o (pipe_rx1_start_block),
    .pipe_rx1_syncheader_o (pipe_rx1_syncheader),
    .pipe_rx1_polarity_i (pipe_rx1_polarity),
    .pipe_rx1_eqcontrol_i (pipe_rx1_eqcontrol),
    .pipe_rx1_eqlplffs_i (pipe_rx1_eqlp_lffs),
    .pipe_rx1_eqlptxpreset_i (pipe_rx1_eqlp_txpreset),
    .pipe_rx1_eqpreset_i (pipe_rx1_eqpreset),
    .pipe_tx1_eqcoeff_o (pipe_tx1_eqcoeff),
    .pipe_tx1_eqdone_o (pipe_tx1_eqdone),
    .pipe_tx1_compliance_i (pipe_tx1_compliance),
    .pipe_tx1_char_is_k_i (pipe_tx1_char_is_k),
    .pipe_tx1_data_i (pipe_tx1_data),
    .pipe_tx1_elec_idle_i (pipe_tx1_elec_idle),
    .pipe_tx1_powerdown_i (pipe_tx1_powerdown),
    .pipe_tx1_datavalid_i (pipe_tx1_data_valid),
    .pipe_tx1_startblock_i (pipe_tx1_start_block),
    .pipe_tx1_syncheader_i (pipe_tx1_syncheader),
    .pipe_tx1_eqcontrol_i (pipe_tx1_eqcontrol),
    .pipe_tx1_eqdeemph_i (pipe_tx1_eqdeemph),
    .pipe_tx1_eqpreset_i (pipe_tx1_eqpreset),
    .pipe_rx1_char_is_k_i (pipe_rx1_char_is_k_gt),
    .pipe_rx1_data_i (pipe_rx1_data_gt),
    .pipe_rx1_valid_i (pipe_rx1_valid_gt),
    .pipe_rx1_data_valid_i (pipe_rx1_data_valid_gt),
    .pipe_rx1_status_i (pipe_rx1_status_gt),
    .pipe_rx1_phy_status_i (pipe_rx1_phy_status_gt),
    .pipe_rx1_elec_idle_i (pipe_rx1_elec_idle_gt),
    .pipe_rx1_eqdone_i (pipe_rx1_eqdone_gt),
    .pipe_rx1_eqlpadaptdone_i (pipe_rx1_eqlp_adaptdone_gt),
    .pipe_rx1_eqlplffssel_i (pipe_rx1_eqlp_lffs_sel_gt),
    .pipe_rx1_eqlpnewtxcoefforpreset_i (pipe_rx1_eqlp_new_txcoef_forpreset_gt),
    .pipe_rx1_startblock_i (pipe_rx1_start_block_gt),
    .pipe_rx1_syncheader_i (pipe_rx1_syncheader_gt),
    .pipe_rx1_polarity_o (pipe_rx1_polarity_gt),
    .pipe_rx1_eqcontrol_o (pipe_rx1_eqcontrol_gt),
    .pipe_rx1_eqlplffs_o (pipe_rx1_eqlp_lffs_gt),
    .pipe_rx1_eqlptxpreset_o (pipe_rx1_eqlp_txpreset_gt),
    .pipe_rx1_eqpreset_o (pipe_rx1_eqpreset_gt),
    .pipe_tx1_eqcoeff_i (pipe_tx1_eqcoeff_gt),
    .pipe_tx1_eqdone_i (pipe_tx1_eqdone_gt),
    .pipe_tx1_compliance_o (pipe_tx1_compliance_gt),
    .pipe_tx1_char_is_k_o (pipe_tx1_char_is_k_gt),
    .pipe_tx1_data_o (pipe_tx1_data_gt),
    .pipe_tx1_elec_idle_o (pipe_tx1_elec_idle_gt),
    .pipe_tx1_powerdown_o (pipe_tx1_powerdown_gt),
    .pipe_tx1_datavalid_o (pipe_tx1_data_valid_gt),
    .pipe_tx1_startblock_o (pipe_tx1_start_block_gt),
    .pipe_tx1_syncheader_o (pipe_tx1_syncheader_gt),
    .pipe_tx1_eqcontrol_o (pipe_tx1_eqcontrol_gt),
    .pipe_tx1_eqdeemph_o (pipe_tx1_eqdeemph_gt),
    .pipe_tx1_eqpreset_o (pipe_tx1_eqpreset_gt),
    .pipe_rx2_char_is_k_o (pipe_rx2_char_is_k),
    .pipe_rx2_data_o (pipe_rx2_data),
    .pipe_rx2_valid_o (pipe_rx2_valid),
    .pipe_rx2_data_valid_o (pipe_rx2_data_valid),
    .pipe_rx2_status_o (pipe_rx2_status),
    .pipe_rx2_phy_status_o (pipe_rx2_phy_status),
    .pipe_rx2_elec_idle_o (pipe_rx2_elec_idle),
    .pipe_rx2_eqdone_o (pipe_rx2_eqdone),
    .pipe_rx2_eqlpadaptdone_o (pipe_rx2_eqlp_adaptdone),
    .pipe_rx2_eqlplffssel_o (pipe_rx2_eqlp_lffs_sel),
    .pipe_rx2_eqlpnewtxcoefforpreset_o (pipe_rx2_eqlp_new_txcoef_forpreset),
    .pipe_rx2_startblock_o (pipe_rx2_start_block),
    .pipe_rx2_syncheader_o (pipe_rx2_syncheader),
    .pipe_rx2_polarity_i (pipe_rx2_polarity),
    .pipe_rx2_eqcontrol_i (pipe_rx2_eqcontrol),
    .pipe_rx2_eqlplffs_i (pipe_rx2_eqlp_lffs),
    .pipe_rx2_eqlptxpreset_i (pipe_rx2_eqlp_txpreset),
    .pipe_rx2_eqpreset_i (pipe_rx2_eqpreset),
    .pipe_tx2_eqcoeff_o (pipe_tx2_eqcoeff),
    .pipe_tx2_eqdone_o (pipe_tx2_eqdone),
    .pipe_tx2_compliance_i (pipe_tx2_compliance),
    .pipe_tx2_char_is_k_i (pipe_tx2_char_is_k),
    .pipe_tx2_data_i (pipe_tx2_data),
    .pipe_tx2_elec_idle_i (pipe_tx2_elec_idle),
    .pipe_tx2_powerdown_i (pipe_tx2_powerdown),
    .pipe_tx2_datavalid_i (pipe_tx2_data_valid),
    .pipe_tx2_startblock_i (pipe_tx2_start_block),
    .pipe_tx2_syncheader_i (pipe_tx2_syncheader),
    .pipe_tx2_eqcontrol_i (pipe_tx2_eqcontrol),
    .pipe_tx2_eqdeemph_i (pipe_tx2_eqdeemph),
    .pipe_tx2_eqpreset_i (pipe_tx2_eqpreset),
    .pipe_rx2_char_is_k_i (pipe_rx2_char_is_k_gt),
    .pipe_rx2_data_i (pipe_rx2_data_gt),
    .pipe_rx2_valid_i (pipe_rx2_valid_gt),
    .pipe_rx2_data_valid_i (pipe_rx2_data_valid_gt),
    .pipe_rx2_status_i (pipe_rx2_status_gt),
    .pipe_rx2_phy_status_i (pipe_rx2_phy_status_gt),
    .pipe_rx2_elec_idle_i (pipe_rx2_elec_idle_gt),
    .pipe_rx2_eqdone_i (pipe_rx2_eqdone_gt),
    .pipe_rx2_eqlpadaptdone_i (pipe_rx2_eqlp_adaptdone_gt),
    .pipe_rx2_eqlplffssel_i (pipe_rx2_eqlp_lffs_sel_gt),
    .pipe_rx2_eqlpnewtxcoefforpreset_i (pipe_rx2_eqlp_new_txcoef_forpreset_gt),
    .pipe_rx2_startblock_i (pipe_rx2_start_block_gt),
    .pipe_rx2_syncheader_i (pipe_rx2_syncheader_gt),
    .pipe_rx2_polarity_o (pipe_rx2_polarity_gt),
    .pipe_rx2_eqcontrol_o (pipe_rx2_eqcontrol_gt),
    .pipe_rx2_eqlplffs_o (pipe_rx2_eqlp_lffs_gt),
    .pipe_rx2_eqlptxpreset_o (pipe_rx2_eqlp_txpreset_gt),
    .pipe_rx2_eqpreset_o (pipe_rx2_eqpreset_gt),
    .pipe_tx2_eqcoeff_i (pipe_tx2_eqcoeff_gt),
    .pipe_tx2_eqdone_i (pipe_tx2_eqdone_gt),
    .pipe_tx2_compliance_o (pipe_tx2_compliance_gt),
    .pipe_tx2_char_is_k_o (pipe_tx2_char_is_k_gt),
    .pipe_tx2_data_o (pipe_tx2_data_gt),
    .pipe_tx2_elec_idle_o (pipe_tx2_elec_idle_gt),
    .pipe_tx2_powerdown_o (pipe_tx2_powerdown_gt),
    .pipe_tx2_datavalid_o (pipe_tx2_data_valid_gt),
    .pipe_tx2_startblock_o (pipe_tx2_start_block_gt),
    .pipe_tx2_syncheader_o (pipe_tx2_syncheader_gt),
    .pipe_tx2_eqcontrol_o (pipe_tx2_eqcontrol_gt),
    .pipe_tx2_eqdeemph_o (pipe_tx2_eqdeemph_gt),
    .pipe_tx2_eqpreset_o (pipe_tx2_eqpreset_gt),
    .pipe_rx3_char_is_k_o (pipe_rx3_char_is_k),
    .pipe_rx3_data_o (pipe_rx3_data),
    .pipe_rx3_valid_o (pipe_rx3_valid),
    .pipe_rx3_data_valid_o (pipe_rx3_data_valid),
    .pipe_rx3_status_o (pipe_rx3_status),
    .pipe_rx3_phy_status_o (pipe_rx3_phy_status),
    .pipe_rx3_elec_idle_o (pipe_rx3_elec_idle),
    .pipe_rx3_eqdone_o (pipe_rx3_eqdone),
    .pipe_rx3_eqlpadaptdone_o (pipe_rx3_eqlp_adaptdone),
    .pipe_rx3_eqlplffssel_o (pipe_rx3_eqlp_lffs_sel),
    .pipe_rx3_eqlpnewtxcoefforpreset_o (pipe_rx3_eqlp_new_txcoef_forpreset),
    .pipe_rx3_startblock_o (pipe_rx3_start_block),
    .pipe_rx3_syncheader_o (pipe_rx3_syncheader),
    .pipe_rx3_polarity_i (pipe_rx3_polarity),
    .pipe_rx3_eqcontrol_i (pipe_rx3_eqcontrol),
    .pipe_rx3_eqlplffs_i (pipe_rx3_eqlp_lffs),
    .pipe_rx3_eqlptxpreset_i (pipe_rx3_eqlp_txpreset),
    .pipe_rx3_eqpreset_i (pipe_rx3_eqpreset),
    .pipe_tx3_eqcoeff_o (pipe_tx3_eqcoeff),
    .pipe_tx3_eqdone_o (pipe_tx3_eqdone),
    .pipe_tx3_compliance_i (pipe_tx3_compliance),
    .pipe_tx3_char_is_k_i (pipe_tx3_char_is_k),
    .pipe_tx3_data_i (pipe_tx3_data),
    .pipe_tx3_elec_idle_i (pipe_tx3_elec_idle),
    .pipe_tx3_powerdown_i (pipe_tx3_powerdown),
    .pipe_tx3_datavalid_i (pipe_tx3_data_valid),
    .pipe_tx3_startblock_i (pipe_tx3_start_block),
    .pipe_tx3_syncheader_i (pipe_tx3_syncheader),
    .pipe_tx3_eqcontrol_i (pipe_tx3_eqcontrol),
    .pipe_tx3_eqdeemph_i (pipe_tx3_eqdeemph),
    .pipe_tx3_eqpreset_i (pipe_tx3_eqpreset),
    .pipe_rx3_char_is_k_i (pipe_rx3_char_is_k_gt),
    .pipe_rx3_data_i (pipe_rx3_data_gt),
    .pipe_rx3_valid_i (pipe_rx3_valid_gt),
    .pipe_rx3_data_valid_i (pipe_rx3_data_valid_gt),
    .pipe_rx3_status_i (pipe_rx3_status_gt),
    .pipe_rx3_phy_status_i (pipe_rx3_phy_status_gt),
    .pipe_rx3_elec_idle_i (pipe_rx3_elec_idle_gt),
    .pipe_rx3_eqdone_i (pipe_rx3_eqdone_gt),
    .pipe_rx3_eqlpadaptdone_i (pipe_rx3_eqlp_adaptdone_gt),
    .pipe_rx3_eqlplffssel_i (pipe_rx3_eqlp_lffs_sel_gt),
    .pipe_rx3_eqlpnewtxcoefforpreset_i (pipe_rx3_eqlp_new_txcoef_forpreset_gt),
    .pipe_rx3_startblock_i (pipe_rx3_start_block_gt),
    .pipe_rx3_syncheader_i (pipe_rx3_syncheader_gt),
    .pipe_rx3_polarity_o (pipe_rx3_polarity_gt),
    .pipe_rx3_eqcontrol_o (pipe_rx3_eqcontrol_gt),
    .pipe_rx3_eqlplffs_o (pipe_rx3_eqlp_lffs_gt),
    .pipe_rx3_eqlptxpreset_o (pipe_rx3_eqlp_txpreset_gt),
    .pipe_rx3_eqpreset_o (pipe_rx3_eqpreset_gt),
    .pipe_tx3_eqcoeff_i (pipe_tx3_eqcoeff_gt),
    .pipe_tx3_eqdone_i (pipe_tx3_eqdone_gt),
    .pipe_tx3_compliance_o (pipe_tx3_compliance_gt),
    .pipe_tx3_char_is_k_o (pipe_tx3_char_is_k_gt),
    .pipe_tx3_data_o (pipe_tx3_data_gt),
    .pipe_tx3_elec_idle_o (pipe_tx3_elec_idle_gt),
    .pipe_tx3_powerdown_o (pipe_tx3_powerdown_gt),
    .pipe_tx3_datavalid_o (pipe_tx3_data_valid_gt),
    .pipe_tx3_startblock_o (pipe_tx3_start_block_gt),
    .pipe_tx3_syncheader_o (pipe_tx3_syncheader_gt),
    .pipe_tx3_eqcontrol_o (pipe_tx3_eqcontrol_gt),
    .pipe_tx3_eqdeemph_o (pipe_tx3_eqdeemph_gt),
    .pipe_tx3_eqpreset_o (pipe_tx3_eqpreset_gt),
    .pipe_rx4_char_is_k_o (pipe_rx4_char_is_k),
    .pipe_rx4_data_o (pipe_rx4_data),
    .pipe_rx4_valid_o (pipe_rx4_valid),
    .pipe_rx4_data_valid_o (pipe_rx4_data_valid),
    .pipe_rx4_status_o (pipe_rx4_status),
    .pipe_rx4_phy_status_o (pipe_rx4_phy_status),
    .pipe_rx4_elec_idle_o (pipe_rx4_elec_idle),
    .pipe_rx4_eqdone_o (pipe_rx4_eqdone),
    .pipe_rx4_eqlpadaptdone_o (pipe_rx4_eqlp_adaptdone),
    .pipe_rx4_eqlplffssel_o (pipe_rx4_eqlp_lffs_sel),
    .pipe_rx4_eqlpnewtxcoefforpreset_o (pipe_rx4_eqlp_new_txcoef_forpreset),
    .pipe_rx4_startblock_o (pipe_rx4_start_block),
    .pipe_rx4_syncheader_o (pipe_rx4_syncheader),
    .pipe_rx4_polarity_i (pipe_rx4_polarity),
    .pipe_rx4_eqcontrol_i (pipe_rx4_eqcontrol),
    .pipe_rx4_eqlplffs_i (pipe_rx4_eqlp_lffs),
    .pipe_rx4_eqlptxpreset_i (pipe_rx4_eqlp_txpreset),
    .pipe_rx4_eqpreset_i (pipe_rx4_eqpreset),
    .pipe_tx4_eqcoeff_o (pipe_tx4_eqcoeff),
    .pipe_tx4_eqdone_o (pipe_tx4_eqdone),
    .pipe_tx4_compliance_i (pipe_tx4_compliance),
    .pipe_tx4_char_is_k_i (pipe_tx4_char_is_k),
    .pipe_tx4_data_i (pipe_tx4_data),
    .pipe_tx4_elec_idle_i (pipe_tx4_elec_idle),
    .pipe_tx4_powerdown_i (pipe_tx4_powerdown),
    .pipe_tx4_datavalid_i (pipe_tx4_data_valid),
    .pipe_tx4_startblock_i (pipe_tx4_start_block),
    .pipe_tx4_syncheader_i (pipe_tx4_syncheader),
    .pipe_tx4_eqcontrol_i (pipe_tx4_eqcontrol),
    .pipe_tx4_eqdeemph_i (pipe_tx4_eqdeemph),
    .pipe_tx4_eqpreset_i (pipe_tx4_eqpreset),
    .pipe_rx4_char_is_k_i (pipe_rx4_char_is_k_gt),
    .pipe_rx4_data_i (pipe_rx4_data_gt),
    .pipe_rx4_valid_i (pipe_rx4_valid_gt),
    .pipe_rx4_data_valid_i (pipe_rx4_data_valid_gt),
    .pipe_rx4_status_i (pipe_rx4_status_gt),
    .pipe_rx4_phy_status_i (pipe_rx4_phy_status_gt),
    .pipe_rx4_elec_idle_i (pipe_rx4_elec_idle_gt),
    .pipe_rx4_eqdone_i (pipe_rx4_eqdone_gt),
    .pipe_rx4_eqlpadaptdone_i (pipe_rx4_eqlp_adaptdone_gt),
    .pipe_rx4_eqlplffssel_i (pipe_rx4_eqlp_lffs_sel_gt),
    .pipe_rx4_eqlpnewtxcoefforpreset_i (pipe_rx4_eqlp_new_txcoef_forpreset_gt),
    .pipe_rx4_startblock_i (pipe_rx4_start_block_gt),
    .pipe_rx4_syncheader_i (pipe_rx4_syncheader_gt),
    .pipe_rx4_polarity_o (pipe_rx4_polarity_gt),
    .pipe_rx4_eqcontrol_o (pipe_rx4_eqcontrol_gt),
    .pipe_rx4_eqlplffs_o (pipe_rx4_eqlp_lffs_gt),
    .pipe_rx4_eqlptxpreset_o (pipe_rx4_eqlp_txpreset_gt),
    .pipe_rx4_eqpreset_o (pipe_rx4_eqpreset_gt),
    .pipe_tx4_eqcoeff_i (pipe_tx4_eqcoeff_gt),
    .pipe_tx4_eqdone_i (pipe_tx4_eqdone_gt),
    .pipe_tx4_compliance_o (pipe_tx4_compliance_gt),
    .pipe_tx4_char_is_k_o (pipe_tx4_char_is_k_gt),
    .pipe_tx4_data_o (pipe_tx4_data_gt),
    .pipe_tx4_elec_idle_o (pipe_tx4_elec_idle_gt),
    .pipe_tx4_powerdown_o (pipe_tx4_powerdown_gt),
    .pipe_tx4_datavalid_o (pipe_tx4_data_valid_gt),
    .pipe_tx4_startblock_o (pipe_tx4_start_block_gt),
    .pipe_tx4_syncheader_o (pipe_tx4_syncheader_gt),
    .pipe_tx4_eqcontrol_o (pipe_tx4_eqcontrol_gt),
    .pipe_tx4_eqdeemph_o (pipe_tx4_eqdeemph_gt),
    .pipe_tx4_eqpreset_o (pipe_tx4_eqpreset_gt),
    .pipe_rx5_char_is_k_o (pipe_rx5_char_is_k),
    .pipe_rx5_data_o (pipe_rx5_data),
    .pipe_rx5_valid_o (pipe_rx5_valid),
    .pipe_rx5_data_valid_o (pipe_rx5_data_valid),
    .pipe_rx5_status_o (pipe_rx5_status),
    .pipe_rx5_phy_status_o (pipe_rx5_phy_status),
    .pipe_rx5_elec_idle_o (pipe_rx5_elec_idle),
    .pipe_rx5_eqdone_o (pipe_rx5_eqdone),
    .pipe_rx5_eqlpadaptdone_o (pipe_rx5_eqlp_adaptdone),
    .pipe_rx5_eqlplffssel_o (pipe_rx5_eqlp_lffs_sel),
    .pipe_rx5_eqlpnewtxcoefforpreset_o (pipe_rx5_eqlp_new_txcoef_forpreset),
    .pipe_rx5_startblock_o (pipe_rx5_start_block),
    .pipe_rx5_syncheader_o (pipe_rx5_syncheader),
    .pipe_rx5_polarity_i (pipe_rx5_polarity),
    .pipe_rx5_eqcontrol_i (pipe_rx5_eqcontrol),
    .pipe_rx5_eqlplffs_i (pipe_rx5_eqlp_lffs),
    .pipe_rx5_eqlptxpreset_i (pipe_rx5_eqlp_txpreset),
    .pipe_rx5_eqpreset_i (pipe_rx5_eqpreset),
    .pipe_tx5_eqcoeff_o (pipe_tx5_eqcoeff),
    .pipe_tx5_eqdone_o (pipe_tx5_eqdone),
    .pipe_tx5_compliance_i (pipe_tx5_compliance),
    .pipe_tx5_char_is_k_i (pipe_tx5_char_is_k),
    .pipe_tx5_data_i (pipe_tx5_data),
    .pipe_tx5_elec_idle_i (pipe_tx5_elec_idle),
    .pipe_tx5_powerdown_i (pipe_tx5_powerdown),
    .pipe_tx5_datavalid_i (pipe_tx5_data_valid),
    .pipe_tx5_startblock_i (pipe_tx5_start_block),
    .pipe_tx5_syncheader_i (pipe_tx5_syncheader),
    .pipe_tx5_eqcontrol_i (pipe_tx5_eqcontrol),
    .pipe_tx5_eqdeemph_i (pipe_tx5_eqdeemph),
    .pipe_tx5_eqpreset_i (pipe_tx5_eqpreset),
    .pipe_rx5_char_is_k_i (pipe_rx5_char_is_k_gt),
    .pipe_rx5_data_i (pipe_rx5_data_gt),
    .pipe_rx5_valid_i (pipe_rx5_valid_gt),
    .pipe_rx5_data_valid_i (pipe_rx5_data_valid_gt),
    .pipe_rx5_status_i (pipe_rx5_status_gt),
    .pipe_rx5_phy_status_i (pipe_rx5_phy_status_gt),
    .pipe_rx5_elec_idle_i (pipe_rx5_elec_idle_gt),
    .pipe_rx5_eqdone_i (pipe_rx5_eqdone_gt),
    .pipe_rx5_eqlpadaptdone_i (pipe_rx5_eqlp_adaptdone_gt),
    .pipe_rx5_eqlplffssel_i (pipe_rx5_eqlp_lffs_sel_gt),
    .pipe_rx5_eqlpnewtxcoefforpreset_i (pipe_rx5_eqlp_new_txcoef_forpreset_gt),
    .pipe_rx5_startblock_i (pipe_rx5_start_block_gt),
    .pipe_rx5_syncheader_i (pipe_rx5_syncheader_gt),
    .pipe_rx5_polarity_o (pipe_rx5_polarity_gt),
    .pipe_rx5_eqcontrol_o (pipe_rx5_eqcontrol_gt),
    .pipe_rx5_eqlplffs_o (pipe_rx5_eqlp_lffs_gt),
    .pipe_rx5_eqlptxpreset_o (pipe_rx5_eqlp_txpreset_gt),
    .pipe_rx5_eqpreset_o (pipe_rx5_eqpreset_gt),
    .pipe_tx5_eqcoeff_i (pipe_tx5_eqcoeff_gt),
    .pipe_tx5_eqdone_i (pipe_tx5_eqdone_gt),
    .pipe_tx5_compliance_o (pipe_tx5_compliance_gt),
    .pipe_tx5_char_is_k_o (pipe_tx5_char_is_k_gt),
    .pipe_tx5_data_o (pipe_tx5_data_gt),
    .pipe_tx5_elec_idle_o (pipe_tx5_elec_idle_gt),
    .pipe_tx5_powerdown_o (pipe_tx5_powerdown_gt),
    .pipe_tx5_datavalid_o (pipe_tx5_data_valid_gt),
    .pipe_tx5_startblock_o (pipe_tx5_start_block_gt),
    .pipe_tx5_syncheader_o (pipe_tx5_syncheader_gt),
    .pipe_tx5_eqcontrol_o (pipe_tx5_eqcontrol_gt),
    .pipe_tx5_eqdeemph_o (pipe_tx5_eqdeemph_gt),
    .pipe_tx5_eqpreset_o (pipe_tx5_eqpreset_gt),
    .pipe_rx6_char_is_k_o (pipe_rx6_char_is_k),
    .pipe_rx6_data_o (pipe_rx6_data),
    .pipe_rx6_valid_o (pipe_rx6_valid),
    .pipe_rx6_data_valid_o (pipe_rx6_data_valid),
    .pipe_rx6_status_o (pipe_rx6_status),
    .pipe_rx6_phy_status_o (pipe_rx6_phy_status),
    .pipe_rx6_elec_idle_o (pipe_rx6_elec_idle),
    .pipe_rx6_eqdone_o (pipe_rx6_eqdone),
    .pipe_rx6_eqlpadaptdone_o (pipe_rx6_eqlp_adaptdone),
    .pipe_rx6_eqlplffssel_o (pipe_rx6_eqlp_lffs_sel),
    .pipe_rx6_eqlpnewtxcoefforpreset_o (pipe_rx6_eqlp_new_txcoef_forpreset),
    .pipe_rx6_startblock_o (pipe_rx6_start_block),
    .pipe_rx6_syncheader_o (pipe_rx6_syncheader),
    .pipe_rx6_polarity_i (pipe_rx6_polarity),
    .pipe_rx6_eqcontrol_i (pipe_rx6_eqcontrol),
    .pipe_rx6_eqlplffs_i (pipe_rx6_eqlp_lffs),
    .pipe_rx6_eqlptxpreset_i (pipe_rx6_eqlp_txpreset),
    .pipe_rx6_eqpreset_i (pipe_rx6_eqpreset),
    .pipe_tx6_eqcoeff_o (pipe_tx6_eqcoeff),
    .pipe_tx6_eqdone_o (pipe_tx6_eqdone),
    .pipe_tx6_compliance_i (pipe_tx6_compliance),
    .pipe_tx6_char_is_k_i (pipe_tx6_char_is_k),
    .pipe_tx6_data_i (pipe_tx6_data),
    .pipe_tx6_elec_idle_i (pipe_tx6_elec_idle),
    .pipe_tx6_powerdown_i (pipe_tx6_powerdown),
    .pipe_tx6_datavalid_i (pipe_tx6_data_valid),
    .pipe_tx6_startblock_i (pipe_tx6_start_block),
    .pipe_tx6_syncheader_i (pipe_tx6_syncheader),
    .pipe_tx6_eqcontrol_i (pipe_tx6_eqcontrol),
    .pipe_tx6_eqdeemph_i (pipe_tx6_eqdeemph),
    .pipe_tx6_eqpreset_i (pipe_tx6_eqpreset),
    .pipe_rx6_char_is_k_i (pipe_rx6_char_is_k_gt),
    .pipe_rx6_data_i (pipe_rx6_data_gt),
    .pipe_rx6_valid_i (pipe_rx6_valid_gt),
    .pipe_rx6_data_valid_i (pipe_rx6_data_valid_gt),
    .pipe_rx6_status_i (pipe_rx6_status_gt),
    .pipe_rx6_phy_status_i (pipe_rx6_phy_status_gt),
    .pipe_rx6_elec_idle_i (pipe_rx6_elec_idle_gt),
    .pipe_rx6_eqdone_i (pipe_rx6_eqdone_gt),
    .pipe_rx6_eqlpadaptdone_i (pipe_rx6_eqlp_adaptdone_gt),
    .pipe_rx6_eqlplffssel_i (pipe_rx6_eqlp_lffs_sel_gt),
    .pipe_rx6_eqlpnewtxcoefforpreset_i (pipe_rx6_eqlp_new_txcoef_forpreset_gt),
    .pipe_rx6_startblock_i (pipe_rx6_start_block_gt),
    .pipe_rx6_syncheader_i (pipe_rx6_syncheader_gt),
    .pipe_rx6_polarity_o (pipe_rx6_polarity_gt),
    .pipe_rx6_eqcontrol_o (pipe_rx6_eqcontrol_gt),
    .pipe_rx6_eqlplffs_o (pipe_rx6_eqlp_lffs_gt),
    .pipe_rx6_eqlptxpreset_o (pipe_rx6_eqlp_txpreset_gt),
    .pipe_rx6_eqpreset_o (pipe_rx6_eqpreset_gt),
    .pipe_tx6_eqcoeff_i (pipe_tx6_eqcoeff_gt),
    .pipe_tx6_eqdone_i (pipe_tx6_eqdone_gt),
    .pipe_tx6_compliance_o (pipe_tx6_compliance_gt),
    .pipe_tx6_char_is_k_o (pipe_tx6_char_is_k_gt),
    .pipe_tx6_data_o (pipe_tx6_data_gt),
    .pipe_tx6_elec_idle_o (pipe_tx6_elec_idle_gt),
    .pipe_tx6_powerdown_o (pipe_tx6_powerdown_gt),
    .pipe_tx6_datavalid_o (pipe_tx6_data_valid_gt),
    .pipe_tx6_startblock_o (pipe_tx6_start_block_gt),
    .pipe_tx6_syncheader_o (pipe_tx6_syncheader_gt),
    .pipe_tx6_eqcontrol_o (pipe_tx6_eqcontrol_gt),
    .pipe_tx6_eqdeemph_o (pipe_tx6_eqdeemph_gt),
    .pipe_tx6_eqpreset_o (pipe_tx6_eqpreset_gt),
    .pipe_rx7_char_is_k_o (pipe_rx7_char_is_k),
    .pipe_rx7_data_o (pipe_rx7_data),
    .pipe_rx7_valid_o (pipe_rx7_valid),
    .pipe_rx7_data_valid_o (pipe_rx7_data_valid),
    .pipe_rx7_status_o (pipe_rx7_status),
    .pipe_rx7_phy_status_o (pipe_rx7_phy_status),
    .pipe_rx7_elec_idle_o (pipe_rx7_elec_idle),
    .pipe_rx7_eqdone_o (pipe_rx7_eqdone),
    .pipe_rx7_eqlpadaptdone_o (pipe_rx7_eqlp_adaptdone),
    .pipe_rx7_eqlplffssel_o (pipe_rx7_eqlp_lffs_sel),
    .pipe_rx7_eqlpnewtxcoefforpreset_o (pipe_rx7_eqlp_new_txcoef_forpreset),
    .pipe_rx7_startblock_o (pipe_rx7_start_block),
    .pipe_rx7_syncheader_o (pipe_rx7_syncheader),
    .pipe_rx7_polarity_i (pipe_rx7_polarity),
    .pipe_rx7_eqcontrol_i (pipe_rx7_eqcontrol),
    .pipe_rx7_eqlplffs_i (pipe_rx7_eqlp_lffs),
    .pipe_rx7_eqlptxpreset_i (pipe_rx7_eqlp_txpreset),
    .pipe_rx7_eqpreset_i (pipe_rx7_eqpreset),
    .pipe_tx7_eqcoeff_o (pipe_tx7_eqcoeff),
    .pipe_tx7_eqdone_o (pipe_tx7_eqdone),
    .pipe_tx7_compliance_i (pipe_tx7_compliance),
    .pipe_tx7_char_is_k_i (pipe_tx7_char_is_k),
    .pipe_tx7_data_i (pipe_tx7_data),
    .pipe_tx7_elec_idle_i (pipe_tx7_elec_idle),
    .pipe_tx7_powerdown_i (pipe_tx7_powerdown),
    .pipe_tx7_datavalid_i (pipe_tx7_data_valid),
    .pipe_tx7_startblock_i (pipe_tx7_start_block),
    .pipe_tx7_syncheader_i (pipe_tx7_syncheader),
    .pipe_tx7_eqcontrol_i (pipe_tx7_eqcontrol),
    .pipe_tx7_eqdeemph_i (pipe_tx7_eqdeemph),
    .pipe_tx7_eqpreset_i (pipe_tx7_eqpreset),
    .pipe_rx7_char_is_k_i (pipe_rx7_char_is_k_gt),
    .pipe_rx7_data_i (pipe_rx7_data_gt),
    .pipe_rx7_valid_i (pipe_rx7_valid_gt),
    .pipe_rx7_data_valid_i (pipe_rx7_data_valid_gt),
    .pipe_rx7_status_i (pipe_rx7_status_gt),
    .pipe_rx7_phy_status_i (pipe_rx7_phy_status_gt),
    .pipe_rx7_elec_idle_i (pipe_rx7_elec_idle_gt),
    .pipe_rx7_eqdone_i (pipe_rx7_eqdone_gt),
    .pipe_rx7_eqlpadaptdone_i (pipe_rx7_eqlp_adaptdone_gt),
    .pipe_rx7_eqlplffssel_i (pipe_rx7_eqlp_lffs_sel_gt),
    .pipe_rx7_eqlpnewtxcoefforpreset_i (pipe_rx7_eqlp_new_txcoef_forpreset_gt),
    .pipe_rx7_startblock_i (pipe_rx7_start_block_gt),
    .pipe_rx7_syncheader_i (pipe_rx7_syncheader_gt),
    .pipe_rx7_polarity_o (pipe_rx7_polarity_gt),
    .pipe_rx7_eqcontrol_o (pipe_rx7_eqcontrol_gt),
    .pipe_rx7_eqlplffs_o (pipe_rx7_eqlp_lffs_gt),
    .pipe_rx7_eqlptxpreset_o (pipe_rx7_eqlp_txpreset_gt),
    .pipe_rx7_eqpreset_o (pipe_rx7_eqpreset_gt),
    .pipe_tx7_eqcoeff_i (pipe_tx7_eqcoeff_gt),
    .pipe_tx7_eqdone_i (pipe_tx7_eqdone_gt),
    .pipe_tx7_compliance_o (pipe_tx7_compliance_gt),
    .pipe_tx7_char_is_k_o (pipe_tx7_char_is_k_gt),
    .pipe_tx7_data_o (pipe_tx7_data_gt),
    .pipe_tx7_elec_idle_o (pipe_tx7_elec_idle_gt),
    .pipe_tx7_powerdown_o (pipe_tx7_powerdown_gt),
    .pipe_tx7_datavalid_o (pipe_tx7_data_valid_gt),
    .pipe_tx7_startblock_o (pipe_tx7_start_block_gt),
    .pipe_tx7_syncheader_o (pipe_tx7_syncheader_gt),
    .pipe_tx7_eqcontrol_o (pipe_tx7_eqcontrol_gt),
    .pipe_tx7_eqdeemph_o (pipe_tx7_eqdeemph_gt),
    .pipe_tx7_eqpreset_o (pipe_tx7_eqpreset_gt)
  );

wire dbg_cfg_local_mgmt_reg_override = 1'b0;


  xdma_x8gen3_pcie3_ip_pcie3_uscale_wrapper 
 #(
    .TCQ (TCQ),
    .NO_DECODE_LOGIC (NO_DECODE_LOGIC),
    .INTERFACE_SPEED (INTERFACE_SPEED),
    .COMPLETION_SPACE (COMPLETION_SPACE),
    .ARI_CAP_ENABLE (ARI_CAP_ENABLE),
    .AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE),
    .AXISTEN_IF_CC_PARITY_CHK (AXISTEN_IF_CC_PARITY_CHK),
    .AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE),
    .AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG),
    .AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE),
    .AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC),
    .AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE),
    .AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE),
    .AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE),
    .AXISTEN_IF_RQ_PARITY_CHK (AXISTEN_IF_RQ_PARITY_CHK),
    .AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH),
    .CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500),
    .CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ),
    .DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE (DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE),
    .DEBUG_PL_DISABLE_EI_INFER_IN_L0 (DEBUG_PL_DISABLE_EI_INFER_IN_L0),
    .DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS),
    .DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM),
    .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT),
    .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN),
    .LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC),
    .LL_CPL_FC_UPDATE_TIMER (LL_CPL_FC_UPDATE_TIMER),
    .LL_CPL_FC_UPDATE_TIMER_OVERRIDE (LL_CPL_FC_UPDATE_TIMER_OVERRIDE),
    .LL_FC_UPDATE_TIMER (LL_FC_UPDATE_TIMER),
    .LL_FC_UPDATE_TIMER_OVERRIDE (LL_FC_UPDATE_TIMER_OVERRIDE),
    .LL_NP_FC_UPDATE_TIMER (LL_NP_FC_UPDATE_TIMER),
    .LL_NP_FC_UPDATE_TIMER_OVERRIDE (LL_NP_FC_UPDATE_TIMER_OVERRIDE),
    .LL_P_FC_UPDATE_TIMER (LL_P_FC_UPDATE_TIMER),
    .LL_P_FC_UPDATE_TIMER_OVERRIDE (LL_P_FC_UPDATE_TIMER_OVERRIDE),
    .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT),
    .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN),
    .LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC),
    .LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL),
    .LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE),
    .LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE),
    .MCAP_CAP_NEXTPTR (MCAP_CAP_NEXTPTR),
    .MCAP_CONFIGURE_OVERRIDE (MCAP_CONFIGURE_OVERRIDE),
    .MCAP_ENABLE (MCAP_ENABLE),
    .MCAP_EOS_DESIGN_SWITCH (MCAP_EOS_DESIGN_SWITCH),
    .MCAP_FPGA_BITSTREAM_VERSION (MCAP_FPGA_BITSTREAM_VERSION),
    .MCAP_GATE_IO_ENABLE_DESIGN_SWITCH (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH),
    .MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH),
    .MCAP_INPUT_GATE_DESIGN_SWITCH (MCAP_INPUT_GATE_DESIGN_SWITCH),
    .MCAP_INTERRUPT_ON_MCAP_EOS (MCAP_INTERRUPT_ON_MCAP_EOS),
    .MCAP_INTERRUPT_ON_MCAP_ERROR (MCAP_INTERRUPT_ON_MCAP_ERROR),
    .MCAP_VSEC_ID (MCAP_VSEC_ID),
    .MCAP_VSEC_LEN (MCAP_VSEC_LEN),
    .MCAP_VSEC_REV (MCAP_VSEC_REV),
    .PF0_AER_CAP_ECRC_CHECK_CAPABLE (PF0_AER_CAP_ECRC_CHECK_CAPABLE),
    .PF0_AER_CAP_ECRC_GEN_CAPABLE (PF0_AER_CAP_ECRC_GEN_CAPABLE),
    .PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR),
    .PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC),
    .PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR),
    .PF0_ARI_CAP_VER (PF0_ARI_CAP_VER),
    .PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE),
    .PF0_BAR0_CONTROL (PF0_BAR0_CONTROL),
    .PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE),
    .PF0_BAR1_CONTROL (PF0_BAR1_CONTROL),
    .PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE),
    .PF0_BAR2_CONTROL (PF0_BAR2_CONTROL),
    .PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE),
    .PF0_BAR3_CONTROL (PF0_BAR3_CONTROL),
    .PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE),
    .PF0_BAR4_CONTROL (PF0_BAR4_CONTROL),
    .PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE),
    .PF0_BAR5_CONTROL (PF0_BAR5_CONTROL),
    .PF0_BIST_REGISTER (PF0_BIST_REGISTER),
    .PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER),
    .PF0_CLASS_CODE (PF0_CLASS_CODE),
    .PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY),
    .PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY),
    .PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED),
    .PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE),
    .PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE),
    .PF0_DEV_CAP2_ARI_FORWARD_ENABLE (PF0_DEV_CAP2_ARI_FORWARD_ENABLE),
    .PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE),
    .PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT),
    .PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT),
    .PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT),
    .PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT),
    .PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT),
    .PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT),
    .PF0_DEVICE_ID (PF0_DEVICE_ID),
    .PF0_DPA_CAP_NEXTPTR (PF0_DPA_CAP_NEXTPTR),
    .PF0_DPA_CAP_SUB_STATE_CONTROL (PF0_DPA_CAP_SUB_STATE_CONTROL),
    .PF0_DPA_CAP_SUB_STATE_CONTROL_EN (PF0_DPA_CAP_SUB_STATE_CONTROL_EN),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
    .PF0_DPA_CAP_VER (PF0_DPA_CAP_VER),
    .PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR),
    .PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE),
    .PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE),
    .PF0_INTERRUPT_LINE (PF0_INTERRUPT_LINE),
    .PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN),
    .PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3),
    .PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG),
    .PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT),
    .PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT),
    .PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR),
    .PF0_LTR_CAP_VER (PF0_LTR_CAP_VER),
    .PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP),
    .PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR),
    .PF0_MSI_CAP_PERVECMASKCAP (PF0_MSI_CAP_PERVECMASKCAP),
    .PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR),
    .PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR),
    .PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET),
    .PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR),
    .PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET),
    .PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE),
    .PF0_PB_CAP_DATA_REG_D0 (PF0_PB_CAP_DATA_REG_D0),
    .PF0_PB_CAP_DATA_REG_D0_SUSTAINED (PF0_PB_CAP_DATA_REG_D0_SUSTAINED),
    .PF0_PB_CAP_DATA_REG_D1 (PF0_PB_CAP_DATA_REG_D1),
    .PF0_PB_CAP_DATA_REG_D3HOT (PF0_PB_CAP_DATA_REG_D3HOT),
    .PF0_PB_CAP_NEXTPTR (PF0_PB_CAP_NEXTPTR),
    .PF0_PB_CAP_SYSTEM_ALLOCATED (PF0_PB_CAP_SYSTEM_ALLOCATED),
    .PF0_PB_CAP_VER (PF0_PB_CAP_VER),
    .PF0_PM_CAP_ID (PF0_PM_CAP_ID),
    .PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR),
    .PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0),
    .PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1),
    .PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT),
    .PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE),
    .PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID),
    .PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET),
    .PF0_RBAR_CAP_ENABLE (PF0_RBAR_CAP_ENABLE),
    .PF0_RBAR_CAP_NEXTPTR (PF0_RBAR_CAP_NEXTPTR),
    .PF0_RBAR_CAP_SIZE0 (PF0_RBAR_CAP_SIZE0),
    .PF0_RBAR_CAP_SIZE1 (PF0_RBAR_CAP_SIZE1),
    .PF0_RBAR_CAP_SIZE2 (PF0_RBAR_CAP_SIZE2),
    .PF0_RBAR_CAP_VER (PF0_RBAR_CAP_VER),
    .PF0_RBAR_CONTROL_INDEX0 (PF0_RBAR_CONTROL_INDEX0),
    .PF0_RBAR_CONTROL_INDEX1 (PF0_RBAR_CONTROL_INDEX1),
    .PF0_RBAR_CONTROL_INDEX2 (PF0_RBAR_CONTROL_INDEX2),
    .PF0_RBAR_CONTROL_SIZE0 (PF0_RBAR_CONTROL_SIZE0),
    .PF0_RBAR_CONTROL_SIZE1 (PF0_RBAR_CONTROL_SIZE1),
    .PF0_RBAR_CONTROL_SIZE2 (PF0_RBAR_CONTROL_SIZE2),
    .PF0_RBAR_NUM (PF0_RBAR_NUM),
    .PF0_REVISION_ID (PF0_REVISION_ID),
    .PF0_SECONDARY_PCIE_CAP_NEXTPTR (PF0_SECONDARY_PCIE_CAP_NEXTPTR),
    .PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE),
    .PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL),
    .PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE),
    .PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL),
    .PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE),
    .PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL),
    .PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE),
    .PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL),
    .PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE),
    .PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL),
    .PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE),
    .PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL),
    .PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF),
    .PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR),
    .PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF),
    .PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER),
    .PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET),
    .PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK),
    .PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE),
    .PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID),
    .PF0_SUBSYSTEM_ID (PF0_SUBSYSTEM_ID),
    .PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE),
    .PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE),
    .PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE),
    .PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR),
    .PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL),
    .PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC),
    .PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE),
    .PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER),
    .PF0_VC_CAP_ENABLE (PF0_VC_CAP_ENABLE),
    .PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR),
    .PF0_VC_CAP_VER (PF0_VC_CAP_VER),
    .PF1_AER_CAP_ECRC_CHECK_CAPABLE (PF1_AER_CAP_ECRC_CHECK_CAPABLE),
    .PF1_AER_CAP_ECRC_GEN_CAPABLE (PF1_AER_CAP_ECRC_GEN_CAPABLE),
    .PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR),
    .PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC),
    .PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR),
    .PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE),
    .PF1_BAR0_CONTROL (PF1_BAR0_CONTROL),
    .PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE),
    .PF1_BAR1_CONTROL (PF1_BAR1_CONTROL),
    .PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE),
    .PF1_BAR2_CONTROL (PF1_BAR2_CONTROL),
    .PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE),
    .PF1_BAR3_CONTROL (PF1_BAR3_CONTROL),
    .PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE),
    .PF1_BAR4_CONTROL (PF1_BAR4_CONTROL),
    .PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE),
    .PF1_BAR5_CONTROL (PF1_BAR5_CONTROL),
    .PF1_BIST_REGISTER (PF1_BIST_REGISTER),
    .PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER),
    .PF1_CLASS_CODE (PF1_CLASS_CODE),
    .PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE),
    .PF1_DEVICE_ID (PF1_DEVICE_ID),
    .PF1_DPA_CAP_NEXTPTR (PF1_DPA_CAP_NEXTPTR),
    .PF1_DPA_CAP_SUB_STATE_CONTROL (PF1_DPA_CAP_SUB_STATE_CONTROL),
    .PF1_DPA_CAP_SUB_STATE_CONTROL_EN (PF1_DPA_CAP_SUB_STATE_CONTROL_EN),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
    .PF1_DPA_CAP_VER (PF1_DPA_CAP_VER),
    .PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR),
    .PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE),
    .PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE),
    .PF1_INTERRUPT_LINE (PF1_INTERRUPT_LINE),
    .PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN),
    .PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP),
    .PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR),
    .PF1_MSI_CAP_PERVECMASKCAP (PF1_MSI_CAP_PERVECMASKCAP),
    .PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR),
    .PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR),
    .PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET),
    .PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR),
    .PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET),
    .PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE),
    .PF1_PB_CAP_DATA_REG_D0 (PF1_PB_CAP_DATA_REG_D0),
    .PF1_PB_CAP_DATA_REG_D0_SUSTAINED (PF1_PB_CAP_DATA_REG_D0_SUSTAINED),
    .PF1_PB_CAP_DATA_REG_D1 (PF1_PB_CAP_DATA_REG_D1),
    .PF1_PB_CAP_DATA_REG_D3HOT (PF1_PB_CAP_DATA_REG_D3HOT),
    .PF1_PB_CAP_NEXTPTR (PF1_PB_CAP_NEXTPTR),
    .PF1_PB_CAP_SYSTEM_ALLOCATED (PF1_PB_CAP_SYSTEM_ALLOCATED),
    .PF1_PB_CAP_VER (PF1_PB_CAP_VER),
    .PF1_PM_CAP_ID (PF1_PM_CAP_ID),
    .PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR),
    .PF1_PM_CAP_VER_ID (PF1_PM_CAP_VER_ID),
    .PF1_RBAR_CAP_ENABLE (PF1_RBAR_CAP_ENABLE),
    .PF1_RBAR_CAP_NEXTPTR (PF1_RBAR_CAP_NEXTPTR),
    .PF1_RBAR_CAP_SIZE0 (PF1_RBAR_CAP_SIZE0),
    .PF1_RBAR_CAP_SIZE1 (PF1_RBAR_CAP_SIZE1),
    .PF1_RBAR_CAP_SIZE2 (PF1_RBAR_CAP_SIZE2),
    .PF1_RBAR_CAP_VER (PF1_RBAR_CAP_VER),
    .PF1_RBAR_CONTROL_INDEX0 (PF1_RBAR_CONTROL_INDEX0),
    .PF1_RBAR_CONTROL_INDEX1 (PF1_RBAR_CONTROL_INDEX1),
    .PF1_RBAR_CONTROL_INDEX2 (PF1_RBAR_CONTROL_INDEX2),
    .PF1_RBAR_CONTROL_SIZE0 (PF1_RBAR_CONTROL_SIZE0),
    .PF1_RBAR_CONTROL_SIZE1 (PF1_RBAR_CONTROL_SIZE1),
    .PF1_RBAR_CONTROL_SIZE2 (PF1_RBAR_CONTROL_SIZE2),
    .PF1_RBAR_NUM (PF1_RBAR_NUM),
    .PF1_REVISION_ID (PF1_REVISION_ID),
    .PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE),
    .PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL),
    .PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE),
    .PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL),
    .PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE),
    .PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL),
    .PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE),
    .PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL),
    .PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE),
    .PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL),
    .PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE),
    .PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL),
    .PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF),
    .PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR),
    .PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF),
    .PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER),
    .PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET),
    .PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK),
    .PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE),
    .PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID),
    .PF1_SUBSYSTEM_ID (PF1_SUBSYSTEM_ID),
    .PF1_TPHR_CAP_DEV_SPECIFIC_MODE (PF1_TPHR_CAP_DEV_SPECIFIC_MODE),
    .PF1_TPHR_CAP_ENABLE (PF1_TPHR_CAP_ENABLE),
    .PF1_TPHR_CAP_INT_VEC_MODE (PF1_TPHR_CAP_INT_VEC_MODE),
    .PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR),
    .PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL),
    .PF1_TPHR_CAP_ST_TABLE_LOC (PF1_TPHR_CAP_ST_TABLE_LOC),
    .PF1_TPHR_CAP_ST_TABLE_SIZE (PF1_TPHR_CAP_ST_TABLE_SIZE),
    .PF1_TPHR_CAP_VER (PF1_TPHR_CAP_VER),
    .PF2_AER_CAP_ECRC_CHECK_CAPABLE (PF2_AER_CAP_ECRC_CHECK_CAPABLE),
    .PF2_AER_CAP_ECRC_GEN_CAPABLE (PF2_AER_CAP_ECRC_GEN_CAPABLE),
    .PF2_AER_CAP_NEXTPTR (PF2_AER_CAP_NEXTPTR),
    .PF2_ARI_CAP_NEXT_FUNC (PF2_ARI_CAP_NEXT_FUNC),
    .PF2_ARI_CAP_NEXTPTR (PF2_ARI_CAP_NEXTPTR),
    .PF2_BAR0_APERTURE_SIZE (PF2_BAR0_APERTURE_SIZE),
    .PF2_BAR0_CONTROL (PF2_BAR0_CONTROL),
    .PF2_BAR1_APERTURE_SIZE (PF2_BAR1_APERTURE_SIZE),
    .PF2_BAR1_CONTROL (PF2_BAR1_CONTROL),
    .PF2_BAR2_APERTURE_SIZE (PF2_BAR2_APERTURE_SIZE),
    .PF2_BAR2_CONTROL (PF2_BAR2_CONTROL),
    .PF2_BAR3_APERTURE_SIZE (PF2_BAR3_APERTURE_SIZE),
    .PF2_BAR3_CONTROL (PF2_BAR3_CONTROL),
    .PF2_BAR4_APERTURE_SIZE (PF2_BAR4_APERTURE_SIZE),
    .PF2_BAR4_CONTROL (PF2_BAR4_CONTROL),
    .PF2_BAR5_APERTURE_SIZE (PF2_BAR5_APERTURE_SIZE),
    .PF2_BAR5_CONTROL (PF2_BAR5_CONTROL),
    .PF2_BIST_REGISTER (PF2_BIST_REGISTER),
    .PF2_CAPABILITY_POINTER (PF2_CAPABILITY_POINTER),
    .PF2_CLASS_CODE (PF2_CLASS_CODE),
    .PF2_DEV_CAP_MAX_PAYLOAD_SIZE (PF2_DEV_CAP_MAX_PAYLOAD_SIZE),
    .PF2_DEVICE_ID (PF2_DEVICE_ID),
    .PF2_DPA_CAP_NEXTPTR (PF2_DPA_CAP_NEXTPTR),
    .PF2_DPA_CAP_SUB_STATE_CONTROL (PF2_DPA_CAP_SUB_STATE_CONTROL),
    .PF2_DPA_CAP_SUB_STATE_CONTROL_EN (PF2_DPA_CAP_SUB_STATE_CONTROL_EN),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
    .PF2_DPA_CAP_VER (PF2_DPA_CAP_VER),
    .PF2_DSN_CAP_NEXTPTR (PF2_DSN_CAP_NEXTPTR),
    .PF2_EXPANSION_ROM_APERTURE_SIZE (PF2_EXPANSION_ROM_APERTURE_SIZE),
    .PF2_EXPANSION_ROM_ENABLE (PF2_EXPANSION_ROM_ENABLE),
    .PF2_INTERRUPT_LINE (PF2_INTERRUPT_LINE),
    .PF2_INTERRUPT_PIN (PF2_INTERRUPT_PIN),
    .PF2_MSI_CAP_MULTIMSGCAP (PF2_MSI_CAP_MULTIMSGCAP),
    .PF2_MSI_CAP_NEXTPTR (PF2_MSI_CAP_NEXTPTR),
    .PF2_MSI_CAP_PERVECMASKCAP (PF2_MSI_CAP_PERVECMASKCAP),
    .PF2_MSIX_CAP_NEXTPTR (PF2_MSIX_CAP_NEXTPTR),
    .PF2_MSIX_CAP_PBA_BIR (PF2_MSIX_CAP_PBA_BIR),
    .PF2_MSIX_CAP_PBA_OFFSET (PF2_MSIX_CAP_PBA_OFFSET),
    .PF2_MSIX_CAP_TABLE_BIR (PF2_MSIX_CAP_TABLE_BIR),
    .PF2_MSIX_CAP_TABLE_OFFSET (PF2_MSIX_CAP_TABLE_OFFSET),
    .PF2_MSIX_CAP_TABLE_SIZE (PF2_MSIX_CAP_TABLE_SIZE),
    .PF2_PB_CAP_DATA_REG_D0 (PF2_PB_CAP_DATA_REG_D0),
    .PF2_PB_CAP_DATA_REG_D0_SUSTAINED (PF2_PB_CAP_DATA_REG_D0_SUSTAINED),
    .PF2_PB_CAP_DATA_REG_D1 (PF2_PB_CAP_DATA_REG_D1),
    .PF2_PB_CAP_DATA_REG_D3HOT (PF2_PB_CAP_DATA_REG_D3HOT),
    .PF2_PB_CAP_NEXTPTR (PF2_PB_CAP_NEXTPTR),
    .PF2_PB_CAP_SYSTEM_ALLOCATED (PF2_PB_CAP_SYSTEM_ALLOCATED),
    .PF2_PB_CAP_VER (PF2_PB_CAP_VER),
    .PF2_PM_CAP_ID (PF2_PM_CAP_ID),
    .PF2_PM_CAP_NEXTPTR (PF2_PM_CAP_NEXTPTR),
    .PF2_PM_CAP_VER_ID (PF2_PM_CAP_VER_ID),
    .PF2_RBAR_CAP_ENABLE (PF2_RBAR_CAP_ENABLE),
    .PF2_RBAR_CAP_NEXTPTR (PF2_RBAR_CAP_NEXTPTR),
    .PF2_RBAR_CAP_SIZE0 (PF2_RBAR_CAP_SIZE0),
    .PF2_RBAR_CAP_SIZE1 (PF2_RBAR_CAP_SIZE1),
    .PF2_RBAR_CAP_SIZE2 (PF2_RBAR_CAP_SIZE2),
    .PF2_RBAR_CAP_VER (PF2_RBAR_CAP_VER),
    .PF2_RBAR_CONTROL_INDEX0 (PF2_RBAR_CONTROL_INDEX0),
    .PF2_RBAR_CONTROL_INDEX1 (PF2_RBAR_CONTROL_INDEX1),
    .PF2_RBAR_CONTROL_INDEX2 (PF2_RBAR_CONTROL_INDEX2),
    .PF2_RBAR_CONTROL_SIZE0 (PF2_RBAR_CONTROL_SIZE0),
    .PF2_RBAR_CONTROL_SIZE1 (PF2_RBAR_CONTROL_SIZE1),
    .PF2_RBAR_CONTROL_SIZE2 (PF2_RBAR_CONTROL_SIZE2),
    .PF2_RBAR_NUM (PF2_RBAR_NUM),
    .PF2_REVISION_ID (PF2_REVISION_ID),
    .PF2_SRIOV_BAR0_APERTURE_SIZE (PF2_SRIOV_BAR0_APERTURE_SIZE),
    .PF2_SRIOV_BAR0_CONTROL (PF2_SRIOV_BAR0_CONTROL),
    .PF2_SRIOV_BAR1_APERTURE_SIZE (PF2_SRIOV_BAR1_APERTURE_SIZE),
    .PF2_SRIOV_BAR1_CONTROL (PF2_SRIOV_BAR1_CONTROL),
    .PF2_SRIOV_BAR2_APERTURE_SIZE (PF2_SRIOV_BAR2_APERTURE_SIZE),
    .PF2_SRIOV_BAR2_CONTROL (PF2_SRIOV_BAR2_CONTROL),
    .PF2_SRIOV_BAR3_APERTURE_SIZE (PF2_SRIOV_BAR3_APERTURE_SIZE),
    .PF2_SRIOV_BAR3_CONTROL (PF2_SRIOV_BAR3_CONTROL),
    .PF2_SRIOV_BAR4_APERTURE_SIZE (PF2_SRIOV_BAR4_APERTURE_SIZE),
    .PF2_SRIOV_BAR4_CONTROL (PF2_SRIOV_BAR4_CONTROL),
    .PF2_SRIOV_BAR5_APERTURE_SIZE (PF2_SRIOV_BAR5_APERTURE_SIZE),
    .PF2_SRIOV_BAR5_CONTROL (PF2_SRIOV_BAR5_CONTROL),
    .PF2_SRIOV_CAP_INITIAL_VF (PF2_SRIOV_CAP_INITIAL_VF),
    .PF2_SRIOV_CAP_NEXTPTR (PF2_SRIOV_CAP_NEXTPTR),
    .PF2_SRIOV_CAP_TOTAL_VF (PF2_SRIOV_CAP_TOTAL_VF),
    .PF2_SRIOV_CAP_VER (PF2_SRIOV_CAP_VER),
    .PF2_SRIOV_FIRST_VF_OFFSET (PF2_SRIOV_FIRST_VF_OFFSET),
    .PF2_SRIOV_FUNC_DEP_LINK (PF2_SRIOV_FUNC_DEP_LINK),
    .PF2_SRIOV_SUPPORTED_PAGE_SIZE (PF2_SRIOV_SUPPORTED_PAGE_SIZE),
    .PF2_SRIOV_VF_DEVICE_ID (PF2_SRIOV_VF_DEVICE_ID),
    .PF2_SUBSYSTEM_ID (PF2_SUBSYSTEM_ID),
    .PF2_TPHR_CAP_DEV_SPECIFIC_MODE (PF2_TPHR_CAP_DEV_SPECIFIC_MODE),
    .PF2_TPHR_CAP_ENABLE (PF2_TPHR_CAP_ENABLE),
    .PF2_TPHR_CAP_INT_VEC_MODE (PF2_TPHR_CAP_INT_VEC_MODE),
    .PF2_TPHR_CAP_NEXTPTR (PF2_TPHR_CAP_NEXTPTR),
    .PF2_TPHR_CAP_ST_MODE_SEL (PF2_TPHR_CAP_ST_MODE_SEL),
    .PF2_TPHR_CAP_ST_TABLE_LOC (PF2_TPHR_CAP_ST_TABLE_LOC),
    .PF2_TPHR_CAP_ST_TABLE_SIZE (PF2_TPHR_CAP_ST_TABLE_SIZE),
    .PF2_TPHR_CAP_VER (PF2_TPHR_CAP_VER),
    .PF3_AER_CAP_ECRC_CHECK_CAPABLE (PF3_AER_CAP_ECRC_CHECK_CAPABLE),
    .PF3_AER_CAP_ECRC_GEN_CAPABLE (PF3_AER_CAP_ECRC_GEN_CAPABLE),
    .PF3_AER_CAP_NEXTPTR (PF3_AER_CAP_NEXTPTR),
    .PF3_ARI_CAP_NEXT_FUNC (PF3_ARI_CAP_NEXT_FUNC),
    .PF3_ARI_CAP_NEXTPTR (PF3_ARI_CAP_NEXTPTR),
    .PF3_BAR0_APERTURE_SIZE (PF3_BAR0_APERTURE_SIZE),
    .PF3_BAR0_CONTROL (PF3_BAR0_CONTROL),
    .PF3_BAR1_APERTURE_SIZE (PF3_BAR1_APERTURE_SIZE),
    .PF3_BAR1_CONTROL (PF3_BAR1_CONTROL),
    .PF3_BAR2_APERTURE_SIZE (PF3_BAR2_APERTURE_SIZE),
    .PF3_BAR2_CONTROL (PF3_BAR2_CONTROL),
    .PF3_BAR3_APERTURE_SIZE (PF3_BAR3_APERTURE_SIZE),
    .PF3_BAR3_CONTROL (PF3_BAR3_CONTROL),
    .PF3_BAR4_APERTURE_SIZE (PF3_BAR4_APERTURE_SIZE),
    .PF3_BAR4_CONTROL (PF3_BAR4_CONTROL),
    .PF3_BAR5_APERTURE_SIZE (PF3_BAR5_APERTURE_SIZE),
    .PF3_BAR5_CONTROL (PF3_BAR5_CONTROL),
    .PF3_BIST_REGISTER (PF3_BIST_REGISTER),
    .PF3_CAPABILITY_POINTER (PF3_CAPABILITY_POINTER),
    .PF3_CLASS_CODE (PF3_CLASS_CODE),
    .PF3_DEV_CAP_MAX_PAYLOAD_SIZE (PF3_DEV_CAP_MAX_PAYLOAD_SIZE),
    .PF3_DEVICE_ID (PF3_DEVICE_ID),
    .PF3_DPA_CAP_NEXTPTR (PF3_DPA_CAP_NEXTPTR),
    .PF3_DPA_CAP_SUB_STATE_CONTROL (PF3_DPA_CAP_SUB_STATE_CONTROL),
    .PF3_DPA_CAP_SUB_STATE_CONTROL_EN (PF3_DPA_CAP_SUB_STATE_CONTROL_EN),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
    .PF3_DPA_CAP_VER (PF3_DPA_CAP_VER),
    .PF3_DSN_CAP_NEXTPTR (PF3_DSN_CAP_NEXTPTR),
    .PF3_EXPANSION_ROM_APERTURE_SIZE (PF3_EXPANSION_ROM_APERTURE_SIZE),
    .PF3_EXPANSION_ROM_ENABLE (PF3_EXPANSION_ROM_ENABLE),
    .PF3_INTERRUPT_LINE (PF3_INTERRUPT_LINE),
    .PF3_INTERRUPT_PIN (PF3_INTERRUPT_PIN),
    .PF3_MSI_CAP_MULTIMSGCAP (PF3_MSI_CAP_MULTIMSGCAP),
    .PF3_MSI_CAP_NEXTPTR (PF3_MSI_CAP_NEXTPTR),
    .PF3_MSI_CAP_PERVECMASKCAP (PF3_MSI_CAP_PERVECMASKCAP),
    .PF3_MSIX_CAP_NEXTPTR (PF3_MSIX_CAP_NEXTPTR),
    .PF3_MSIX_CAP_PBA_BIR (PF3_MSIX_CAP_PBA_BIR),
    .PF3_MSIX_CAP_PBA_OFFSET (PF3_MSIX_CAP_PBA_OFFSET),
    .PF3_MSIX_CAP_TABLE_BIR (PF3_MSIX_CAP_TABLE_BIR),
    .PF3_MSIX_CAP_TABLE_OFFSET (PF3_MSIX_CAP_TABLE_OFFSET),
    .PF3_MSIX_CAP_TABLE_SIZE (PF3_MSIX_CAP_TABLE_SIZE),
    .PF3_PB_CAP_DATA_REG_D0 (PF3_PB_CAP_DATA_REG_D0),
    .PF3_PB_CAP_DATA_REG_D0_SUSTAINED (PF3_PB_CAP_DATA_REG_D0_SUSTAINED),
    .PF3_PB_CAP_DATA_REG_D1 (PF3_PB_CAP_DATA_REG_D1),
    .PF3_PB_CAP_DATA_REG_D3HOT (PF3_PB_CAP_DATA_REG_D3HOT),
    .PF3_PB_CAP_NEXTPTR (PF3_PB_CAP_NEXTPTR),
    .PF3_PB_CAP_SYSTEM_ALLOCATED (PF3_PB_CAP_SYSTEM_ALLOCATED),
    .PF3_PB_CAP_VER (PF3_PB_CAP_VER),
    .PF3_PM_CAP_ID (PF3_PM_CAP_ID),
    .PF3_PM_CAP_NEXTPTR (PF3_PM_CAP_NEXTPTR),
    .PF3_PM_CAP_VER_ID (PF3_PM_CAP_VER_ID),
    .PF3_RBAR_CAP_ENABLE (PF3_RBAR_CAP_ENABLE),
    .PF3_RBAR_CAP_NEXTPTR (PF3_RBAR_CAP_NEXTPTR),
    .PF3_RBAR_CAP_SIZE0 (PF3_RBAR_CAP_SIZE0),
    .PF3_RBAR_CAP_SIZE1 (PF3_RBAR_CAP_SIZE1),
    .PF3_RBAR_CAP_SIZE2 (PF3_RBAR_CAP_SIZE2),
    .PF3_RBAR_CAP_VER (PF3_RBAR_CAP_VER),
    .PF3_RBAR_CONTROL_INDEX0 (PF3_RBAR_CONTROL_INDEX0),
    .PF3_RBAR_CONTROL_INDEX1 (PF3_RBAR_CONTROL_INDEX1),
    .PF3_RBAR_CONTROL_INDEX2 (PF3_RBAR_CONTROL_INDEX2),
    .PF3_RBAR_CONTROL_SIZE0 (PF3_RBAR_CONTROL_SIZE0),
    .PF3_RBAR_CONTROL_SIZE1 (PF3_RBAR_CONTROL_SIZE1),
    .PF3_RBAR_CONTROL_SIZE2 (PF3_RBAR_CONTROL_SIZE2),
    .PF3_RBAR_NUM (PF3_RBAR_NUM),
    .PF3_REVISION_ID (PF3_REVISION_ID),
    .PF3_SRIOV_BAR0_APERTURE_SIZE (PF3_SRIOV_BAR0_APERTURE_SIZE),
    .PF3_SRIOV_BAR0_CONTROL (PF3_SRIOV_BAR0_CONTROL),
    .PF3_SRIOV_BAR1_APERTURE_SIZE (PF3_SRIOV_BAR1_APERTURE_SIZE),
    .PF3_SRIOV_BAR1_CONTROL (PF3_SRIOV_BAR1_CONTROL),
    .PF3_SRIOV_BAR2_APERTURE_SIZE (PF3_SRIOV_BAR2_APERTURE_SIZE),
    .PF3_SRIOV_BAR2_CONTROL (PF3_SRIOV_BAR2_CONTROL),
    .PF3_SRIOV_BAR3_APERTURE_SIZE (PF3_SRIOV_BAR3_APERTURE_SIZE),
    .PF3_SRIOV_BAR3_CONTROL (PF3_SRIOV_BAR3_CONTROL),
    .PF3_SRIOV_BAR4_APERTURE_SIZE (PF3_SRIOV_BAR4_APERTURE_SIZE),
    .PF3_SRIOV_BAR4_CONTROL (PF3_SRIOV_BAR4_CONTROL),
    .PF3_SRIOV_BAR5_APERTURE_SIZE (PF3_SRIOV_BAR5_APERTURE_SIZE),
    .PF3_SRIOV_BAR5_CONTROL (PF3_SRIOV_BAR5_CONTROL),
    .PF3_SRIOV_CAP_INITIAL_VF (PF3_SRIOV_CAP_INITIAL_VF),
    .PF3_SRIOV_CAP_NEXTPTR (PF3_SRIOV_CAP_NEXTPTR),
    .PF3_SRIOV_CAP_TOTAL_VF (PF3_SRIOV_CAP_TOTAL_VF),
    .PF3_SRIOV_CAP_VER (PF3_SRIOV_CAP_VER),
    .PF3_SRIOV_FIRST_VF_OFFSET (PF3_SRIOV_FIRST_VF_OFFSET),
    .PF3_SRIOV_FUNC_DEP_LINK (PF3_SRIOV_FUNC_DEP_LINK),
    .PF3_SRIOV_SUPPORTED_PAGE_SIZE (PF3_SRIOV_SUPPORTED_PAGE_SIZE),
    .PF3_SRIOV_VF_DEVICE_ID (PF3_SRIOV_VF_DEVICE_ID),
    .PF3_SUBSYSTEM_ID (PF3_SUBSYSTEM_ID),
    .PF3_TPHR_CAP_DEV_SPECIFIC_MODE (PF3_TPHR_CAP_DEV_SPECIFIC_MODE),
    .PF3_TPHR_CAP_ENABLE (PF3_TPHR_CAP_ENABLE),
    .PF3_TPHR_CAP_INT_VEC_MODE (PF3_TPHR_CAP_INT_VEC_MODE),
    .PF3_TPHR_CAP_NEXTPTR (PF3_TPHR_CAP_NEXTPTR),
    .PF3_TPHR_CAP_ST_MODE_SEL (PF3_TPHR_CAP_ST_MODE_SEL),
    .PF3_TPHR_CAP_ST_TABLE_LOC (PF3_TPHR_CAP_ST_TABLE_LOC),
    .PF3_TPHR_CAP_ST_TABLE_SIZE (PF3_TPHR_CAP_ST_TABLE_SIZE),
    .PF3_TPHR_CAP_VER (PF3_TPHR_CAP_VER),
    .PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3),
    .PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2),
    .PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0),
    .PL_DISABLE_GEN3_DC_BALANCE (PL_DISABLE_GEN3_DC_BALANCE),
    .PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP (PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP),
    .PL_DISABLE_RETRAIN_ON_FRAMING_ERROR (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR),
    .PL_DISABLE_SCRAMBLING (PL_DISABLE_SCRAMBLING),
    .PL_DISABLE_SYNC_HEADER_FRAMING_ERROR (PL_DISABLE_SYNC_HEADER_FRAMING_ERROR),
    .PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE),
    .PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK),
    .PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK),
    .PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT),
    .PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT),
    .PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23),
    .PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT (PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT),
    .PL_EQ_DEFAULT_GEN3_TX_PRESET (PL_EQ_DEFAULT_GEN3_TX_PRESET),
    .PL_EQ_PHASE01_RX_ADAPT (PL_EQ_PHASE01_RX_ADAPT),
    .PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE),
    .PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL),
    .PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL),
    .PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL),
    .PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL),
    .PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL),
    .PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL),
    .PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL),
    .PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL),
    .PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED),
    .PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH),
    .PL_N_FTS_COMCLK_GEN1 (PL_N_FTS_COMCLK_GEN1),
    .PL_N_FTS_COMCLK_GEN2 (PL_N_FTS_COMCLK_GEN2),
    .PL_N_FTS_COMCLK_GEN3 (PL_N_FTS_COMCLK_GEN3),
    .PL_N_FTS_GEN1 (PL_N_FTS_GEN1),
    .PL_N_FTS_GEN2 (PL_N_FTS_GEN2),
    .PL_N_FTS_GEN3 (PL_N_FTS_GEN3),
    .PL_REPORT_ALL_PHY_ERRORS (PL_REPORT_ALL_PHY_ERRORS),
  // synthesis translate_off
    .PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING),
  // synthesis translate_on
    .PL_UPSTREAM_FACING (PL_UPSTREAM_FACING),
    .PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT),
    .PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY),
    .PM_ENABLE_L23_ENTRY (PM_ENABLE_L23_ENTRY),
    .PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE),
    .PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY),
    .PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY),
    .PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY),
    .SIM_JTAG_IDCODE (SIM_JTAG_IDCODE),
    .SIM_VERSION (SIM_VERSION),
    .SPARE_BIT0 (SPARE_BIT0),
    .SPARE_BIT1 (SPARE_BIT1),
    .SPARE_BIT2 (SPARE_BIT2),
    .SPARE_BIT3 (SPARE_BIT3),
    .SPARE_BIT4 (SPARE_BIT4),
    .SPARE_BIT5 (SPARE_BIT5),
    .SPARE_BIT6 (SPARE_BIT6),
    .SPARE_BIT7 (SPARE_BIT7),
    .SPARE_BIT8 (SPARE_BIT8),
    .SPARE_BYTE0 (SPARE_BYTE0),
    .SPARE_BYTE1 (SPARE_BYTE1),
    .SPARE_BYTE2 (SPARE_BYTE2),
    .SPARE_BYTE3 (SPARE_BYTE3),
    .SPARE_WORD0 (SPARE_WORD0),
    .SPARE_WORD1 (SPARE_WORD1),
    .SPARE_WORD2 (SPARE_WORD2),
    .SPARE_WORD3 (SPARE_WORD3),
    .SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE),
    .TL_COMPL_TIMEOUT_REG0 (TL_COMPL_TIMEOUT_REG0),
    .TL_COMPL_TIMEOUT_REG1 (TL_COMPL_TIMEOUT_REG1),
    .TL_CREDITS_CD (TL_CREDITS_CD),
    .TL_CREDITS_CH (TL_CREDITS_CH),
    .TL_CREDITS_NPD (TL_CREDITS_NPD),
    .TL_CREDITS_NPH (TL_CREDITS_NPH),
    .TL_CREDITS_PD (TL_CREDITS_PD),
    .TL_CREDITS_PH (TL_CREDITS_PH),
    .TL_ENABLE_MESSAGE_RID_CHECK_ENABLE (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE),
    .TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE),
    .TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE),
    .TL_LEGACY_MODE_ENABLE (TL_LEGACY_MODE_ENABLE),
    .TL_PF_ENABLE_REG (TL_PF_ENABLE_REG),
    .TL_TX_MUX_STRICT_PRIORITY (TL_TX_MUX_STRICT_PRIORITY),
    .TWO_LAYER_MODE_DLCMSM_ENABLE (TWO_LAYER_MODE_DLCMSM_ENABLE),
    .TWO_LAYER_MODE_ENABLE (TWO_LAYER_MODE_ENABLE),
    .TWO_LAYER_MODE_WIDTH_256 (TWO_LAYER_MODE_WIDTH_256),
    .VF0_ARI_CAP_NEXTPTR (VF0_ARI_CAP_NEXTPTR),
    .VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER),
    .VF0_MSI_CAP_MULTIMSGCAP (VF0_MSI_CAP_MULTIMSGCAP),
    .VF0_MSIX_CAP_PBA_BIR (VF0_MSIX_CAP_PBA_BIR),
    .VF0_MSIX_CAP_PBA_OFFSET (VF0_MSIX_CAP_PBA_OFFSET),
    .VF0_MSIX_CAP_TABLE_BIR (VF0_MSIX_CAP_TABLE_BIR),
    .VF0_MSIX_CAP_TABLE_OFFSET (VF0_MSIX_CAP_TABLE_OFFSET),
    .VF0_MSIX_CAP_TABLE_SIZE (VF0_MSIX_CAP_TABLE_SIZE),
    .VF0_PM_CAP_ID (VF0_PM_CAP_ID),
    .VF0_PM_CAP_NEXTPTR (VF0_PM_CAP_NEXTPTR),
    .VF0_PM_CAP_VER_ID (VF0_PM_CAP_VER_ID),
    .VF0_TPHR_CAP_DEV_SPECIFIC_MODE (VF0_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF0_TPHR_CAP_ENABLE (VF0_TPHR_CAP_ENABLE),
    .VF0_TPHR_CAP_INT_VEC_MODE (VF0_TPHR_CAP_INT_VEC_MODE),
    .VF0_TPHR_CAP_NEXTPTR (VF0_TPHR_CAP_NEXTPTR),
    .VF0_TPHR_CAP_ST_MODE_SEL (VF0_TPHR_CAP_ST_MODE_SEL),
    .VF0_TPHR_CAP_ST_TABLE_LOC (VF0_TPHR_CAP_ST_TABLE_LOC),
    .VF0_TPHR_CAP_ST_TABLE_SIZE (VF0_TPHR_CAP_ST_TABLE_SIZE),
    .VF0_TPHR_CAP_VER (VF0_TPHR_CAP_VER),
    .VF1_ARI_CAP_NEXTPTR (VF1_ARI_CAP_NEXTPTR),
    .VF1_MSI_CAP_MULTIMSGCAP (VF1_MSI_CAP_MULTIMSGCAP),
    .VF1_MSIX_CAP_PBA_BIR (VF1_MSIX_CAP_PBA_BIR),
    .VF1_MSIX_CAP_PBA_OFFSET (VF1_MSIX_CAP_PBA_OFFSET),
    .VF1_MSIX_CAP_TABLE_BIR (VF1_MSIX_CAP_TABLE_BIR),
    .VF1_MSIX_CAP_TABLE_OFFSET (VF1_MSIX_CAP_TABLE_OFFSET),
    .VF1_MSIX_CAP_TABLE_SIZE (VF1_MSIX_CAP_TABLE_SIZE),
    .VF1_PM_CAP_ID (VF1_PM_CAP_ID),
    .VF1_PM_CAP_NEXTPTR (VF1_PM_CAP_NEXTPTR),
    .VF1_PM_CAP_VER_ID (VF1_PM_CAP_VER_ID),
    .VF1_TPHR_CAP_DEV_SPECIFIC_MODE (VF1_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF1_TPHR_CAP_ENABLE (VF1_TPHR_CAP_ENABLE),
    .VF1_TPHR_CAP_INT_VEC_MODE (VF1_TPHR_CAP_INT_VEC_MODE),
    .VF1_TPHR_CAP_NEXTPTR (VF1_TPHR_CAP_NEXTPTR),
    .VF1_TPHR_CAP_ST_MODE_SEL (VF1_TPHR_CAP_ST_MODE_SEL),
    .VF1_TPHR_CAP_ST_TABLE_LOC (VF1_TPHR_CAP_ST_TABLE_LOC),
    .VF1_TPHR_CAP_ST_TABLE_SIZE (VF1_TPHR_CAP_ST_TABLE_SIZE),
    .VF1_TPHR_CAP_VER (VF1_TPHR_CAP_VER),
    .VF2_ARI_CAP_NEXTPTR (VF2_ARI_CAP_NEXTPTR),
    .VF2_MSI_CAP_MULTIMSGCAP (VF2_MSI_CAP_MULTIMSGCAP),
    .VF2_MSIX_CAP_PBA_BIR (VF2_MSIX_CAP_PBA_BIR),
    .VF2_MSIX_CAP_PBA_OFFSET (VF2_MSIX_CAP_PBA_OFFSET),
    .VF2_MSIX_CAP_TABLE_BIR (VF2_MSIX_CAP_TABLE_BIR),
    .VF2_MSIX_CAP_TABLE_OFFSET (VF2_MSIX_CAP_TABLE_OFFSET),
    .VF2_MSIX_CAP_TABLE_SIZE (VF2_MSIX_CAP_TABLE_SIZE),
    .VF2_PM_CAP_ID (VF2_PM_CAP_ID),
    .VF2_PM_CAP_NEXTPTR (VF2_PM_CAP_NEXTPTR),
    .VF2_PM_CAP_VER_ID (VF2_PM_CAP_VER_ID),
    .VF2_TPHR_CAP_DEV_SPECIFIC_MODE (VF2_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF2_TPHR_CAP_ENABLE (VF2_TPHR_CAP_ENABLE),
    .VF2_TPHR_CAP_INT_VEC_MODE (VF2_TPHR_CAP_INT_VEC_MODE),
    .VF2_TPHR_CAP_NEXTPTR (VF2_TPHR_CAP_NEXTPTR),
    .VF2_TPHR_CAP_ST_MODE_SEL (VF2_TPHR_CAP_ST_MODE_SEL),
    .VF2_TPHR_CAP_ST_TABLE_LOC (VF2_TPHR_CAP_ST_TABLE_LOC),
    .VF2_TPHR_CAP_ST_TABLE_SIZE (VF2_TPHR_CAP_ST_TABLE_SIZE),
    .VF2_TPHR_CAP_VER (VF2_TPHR_CAP_VER),
    .VF3_ARI_CAP_NEXTPTR (VF3_ARI_CAP_NEXTPTR),
    .VF3_MSI_CAP_MULTIMSGCAP (VF3_MSI_CAP_MULTIMSGCAP),
    .VF3_MSIX_CAP_PBA_BIR (VF3_MSIX_CAP_PBA_BIR),
    .VF3_MSIX_CAP_PBA_OFFSET (VF3_MSIX_CAP_PBA_OFFSET),
    .VF3_MSIX_CAP_TABLE_BIR (VF3_MSIX_CAP_TABLE_BIR),
    .VF3_MSIX_CAP_TABLE_OFFSET (VF3_MSIX_CAP_TABLE_OFFSET),
    .VF3_MSIX_CAP_TABLE_SIZE (VF3_MSIX_CAP_TABLE_SIZE),
    .VF3_PM_CAP_ID (VF3_PM_CAP_ID),
    .VF3_PM_CAP_NEXTPTR (VF3_PM_CAP_NEXTPTR),
    .VF3_PM_CAP_VER_ID (VF3_PM_CAP_VER_ID),
    .VF3_TPHR_CAP_DEV_SPECIFIC_MODE (VF3_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF3_TPHR_CAP_ENABLE (VF3_TPHR_CAP_ENABLE),
    .VF3_TPHR_CAP_INT_VEC_MODE (VF3_TPHR_CAP_INT_VEC_MODE),
    .VF3_TPHR_CAP_NEXTPTR (VF3_TPHR_CAP_NEXTPTR),
    .VF3_TPHR_CAP_ST_MODE_SEL (VF3_TPHR_CAP_ST_MODE_SEL),
    .VF3_TPHR_CAP_ST_TABLE_LOC (VF3_TPHR_CAP_ST_TABLE_LOC),
    .VF3_TPHR_CAP_ST_TABLE_SIZE (VF3_TPHR_CAP_ST_TABLE_SIZE),
    .VF3_TPHR_CAP_VER (VF3_TPHR_CAP_VER),
    .VF4_ARI_CAP_NEXTPTR (VF4_ARI_CAP_NEXTPTR),
    .VF4_MSI_CAP_MULTIMSGCAP (VF4_MSI_CAP_MULTIMSGCAP),
    .VF4_MSIX_CAP_PBA_BIR (VF4_MSIX_CAP_PBA_BIR),
    .VF4_MSIX_CAP_PBA_OFFSET (VF4_MSIX_CAP_PBA_OFFSET),
    .VF4_MSIX_CAP_TABLE_BIR (VF4_MSIX_CAP_TABLE_BIR),
    .VF4_MSIX_CAP_TABLE_OFFSET (VF4_MSIX_CAP_TABLE_OFFSET),
    .VF4_MSIX_CAP_TABLE_SIZE (VF4_MSIX_CAP_TABLE_SIZE),
    .VF4_PM_CAP_ID (VF4_PM_CAP_ID),
    .VF4_PM_CAP_NEXTPTR (VF4_PM_CAP_NEXTPTR),
    .VF4_PM_CAP_VER_ID (VF4_PM_CAP_VER_ID),
    .VF4_TPHR_CAP_DEV_SPECIFIC_MODE (VF4_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF4_TPHR_CAP_ENABLE (VF4_TPHR_CAP_ENABLE),
    .VF4_TPHR_CAP_INT_VEC_MODE (VF4_TPHR_CAP_INT_VEC_MODE),
    .VF4_TPHR_CAP_NEXTPTR (VF4_TPHR_CAP_NEXTPTR),
    .VF4_TPHR_CAP_ST_MODE_SEL (VF4_TPHR_CAP_ST_MODE_SEL),
    .VF4_TPHR_CAP_ST_TABLE_LOC (VF4_TPHR_CAP_ST_TABLE_LOC),
    .VF4_TPHR_CAP_ST_TABLE_SIZE (VF4_TPHR_CAP_ST_TABLE_SIZE),
    .VF4_TPHR_CAP_VER (VF4_TPHR_CAP_VER),
    .VF5_ARI_CAP_NEXTPTR (VF5_ARI_CAP_NEXTPTR),
    .VF5_MSI_CAP_MULTIMSGCAP (VF5_MSI_CAP_MULTIMSGCAP),
    .VF5_MSIX_CAP_PBA_BIR (VF5_MSIX_CAP_PBA_BIR),
    .VF5_MSIX_CAP_PBA_OFFSET (VF5_MSIX_CAP_PBA_OFFSET),
    .VF5_MSIX_CAP_TABLE_BIR (VF5_MSIX_CAP_TABLE_BIR),
    .VF5_MSIX_CAP_TABLE_OFFSET (VF5_MSIX_CAP_TABLE_OFFSET),
    .VF5_MSIX_CAP_TABLE_SIZE (VF5_MSIX_CAP_TABLE_SIZE),
    .VF5_PM_CAP_ID (VF5_PM_CAP_ID),
    .VF5_PM_CAP_NEXTPTR (VF5_PM_CAP_NEXTPTR),
    .VF5_PM_CAP_VER_ID (VF5_PM_CAP_VER_ID),
    .VF5_TPHR_CAP_DEV_SPECIFIC_MODE (VF5_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF5_TPHR_CAP_ENABLE (VF5_TPHR_CAP_ENABLE),
    .VF5_TPHR_CAP_INT_VEC_MODE (VF5_TPHR_CAP_INT_VEC_MODE),
    .VF5_TPHR_CAP_NEXTPTR (VF5_TPHR_CAP_NEXTPTR),
    .VF5_TPHR_CAP_ST_MODE_SEL (VF5_TPHR_CAP_ST_MODE_SEL),
    .VF5_TPHR_CAP_ST_TABLE_LOC (VF5_TPHR_CAP_ST_TABLE_LOC),
    .VF5_TPHR_CAP_ST_TABLE_SIZE (VF5_TPHR_CAP_ST_TABLE_SIZE),
    .VF5_TPHR_CAP_VER (VF5_TPHR_CAP_VER),
    .VF6_ARI_CAP_NEXTPTR (VF6_ARI_CAP_NEXTPTR),
    .VF6_MSI_CAP_MULTIMSGCAP (VF6_MSI_CAP_MULTIMSGCAP),
    .VF6_MSIX_CAP_PBA_BIR (VF6_MSIX_CAP_PBA_BIR),
    .VF6_MSIX_CAP_PBA_OFFSET (VF6_MSIX_CAP_PBA_OFFSET),
    .VF6_MSIX_CAP_TABLE_BIR (VF6_MSIX_CAP_TABLE_BIR),
    .VF6_MSIX_CAP_TABLE_OFFSET (VF6_MSIX_CAP_TABLE_OFFSET),
    .VF6_MSIX_CAP_TABLE_SIZE (VF6_MSIX_CAP_TABLE_SIZE),
    .VF6_PM_CAP_ID (VF6_PM_CAP_ID),
    .VF6_PM_CAP_NEXTPTR (VF6_PM_CAP_NEXTPTR),
    .VF6_PM_CAP_VER_ID (VF6_PM_CAP_VER_ID),
    .VF6_TPHR_CAP_DEV_SPECIFIC_MODE (VF6_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF6_TPHR_CAP_ENABLE (VF6_TPHR_CAP_ENABLE),
    .VF6_TPHR_CAP_INT_VEC_MODE (VF6_TPHR_CAP_INT_VEC_MODE),
    .VF6_TPHR_CAP_NEXTPTR (VF6_TPHR_CAP_NEXTPTR),
    .VF6_TPHR_CAP_ST_MODE_SEL (VF6_TPHR_CAP_ST_MODE_SEL),
    .VF6_TPHR_CAP_ST_TABLE_LOC (VF6_TPHR_CAP_ST_TABLE_LOC),
    .VF6_TPHR_CAP_ST_TABLE_SIZE (VF6_TPHR_CAP_ST_TABLE_SIZE),
    .VF6_TPHR_CAP_VER (VF6_TPHR_CAP_VER),
    .VF7_ARI_CAP_NEXTPTR (VF7_ARI_CAP_NEXTPTR),
    .VF7_MSI_CAP_MULTIMSGCAP (VF7_MSI_CAP_MULTIMSGCAP),
    .VF7_MSIX_CAP_PBA_BIR (VF7_MSIX_CAP_PBA_BIR),
    .VF7_MSIX_CAP_PBA_OFFSET (VF7_MSIX_CAP_PBA_OFFSET),
    .VF7_MSIX_CAP_TABLE_BIR (VF7_MSIX_CAP_TABLE_BIR),
    .VF7_MSIX_CAP_TABLE_OFFSET (VF7_MSIX_CAP_TABLE_OFFSET),
    .VF7_MSIX_CAP_TABLE_SIZE (VF7_MSIX_CAP_TABLE_SIZE),
    .VF7_PM_CAP_ID (VF7_PM_CAP_ID),
    .VF7_PM_CAP_NEXTPTR (VF7_PM_CAP_NEXTPTR),
    .VF7_PM_CAP_VER_ID (VF7_PM_CAP_VER_ID),
    .VF7_TPHR_CAP_DEV_SPECIFIC_MODE (VF7_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF7_TPHR_CAP_ENABLE (VF7_TPHR_CAP_ENABLE),
    .VF7_TPHR_CAP_INT_VEC_MODE (VF7_TPHR_CAP_INT_VEC_MODE),
    .VF7_TPHR_CAP_NEXTPTR (VF7_TPHR_CAP_NEXTPTR),
    .VF7_TPHR_CAP_ST_MODE_SEL (VF7_TPHR_CAP_ST_MODE_SEL),
    .VF7_TPHR_CAP_ST_TABLE_LOC (VF7_TPHR_CAP_ST_TABLE_LOC),
    .VF7_TPHR_CAP_ST_TABLE_SIZE (VF7_TPHR_CAP_ST_TABLE_SIZE),
    .VF7_TPHR_CAP_VER (VF7_TPHR_CAP_VER))
  pcie3_uscale_wrapper_inst (
    .CFGCONFIGSPACEENABLE (cfg_config_space_enable),
    .CFGDEVID (cfg_dev_id),
    .CFGDSBUSNUMBER (cfg_ds_bus_number),
    .CFGDSDEVICENUMBER (cfg_ds_device_number),
    .CFGDSFUNCTIONNUMBER (cfg_ds_function_number),
    .CFGDSN (cfg_dsn),
    .CFGDSPORTNUMBER (cfg_ds_port_number),
    .CFGERRCORIN (cfg_err_cor_in),
    .CFGERRUNCORIN (cfg_err_uncor_in),
    .CFGEXTREADDATA (cfg_ext_read_data),
    .CFGEXTREADDATAVALID (cfg_ext_read_data_valid),
    .CFGFCSEL (cfg_fc_sel),
    .CFGFLRDONE (cfg_flr_done),
    .CFGHOTRESETIN (cfg_hot_reset_in),
    .CFGINTERRUPTINT (cfg_interrupt_int),
    .CFGINTERRUPTMSIATTR (cfg_interrupt_msi_attr),
    .CFGINTERRUPTMSIFUNCTIONNUMBER (cfg_interrupt_msi_function_number),
    .CFGINTERRUPTMSIINT (cfg_interrupt_msi_int),
    .CFGINTERRUPTMSIPENDINGSTATUS (cfg_interrupt_msi_pending_status),
    .CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE (cfg_interrupt_msi_pending_status_data_enable),
    .CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM (cfg_interrupt_msi_pending_status_function_num),
    .CFGINTERRUPTMSISELECT (cfg_interrupt_msi_select),
    .CFGINTERRUPTMSITPHPRESENT (cfg_interrupt_msi_tph_present),
    .CFGINTERRUPTMSITPHSTTAG (cfg_interrupt_msi_tph_st_tag),
    .CFGINTERRUPTMSITPHTYPE (cfg_interrupt_msi_tph_type),
    .CFGINTERRUPTMSIXADDRESS (cfg_interrupt_msix_address),
    .CFGINTERRUPTMSIXDATA (cfg_interrupt_msix_data),
    .CFGINTERRUPTMSIXINT (cfg_interrupt_msix_int),
    .CFGINTERRUPTPENDING (cfg_interrupt_pending),
    .CFGLINKTRAININGENABLE (cfg_link_training_enable),
    .CFGMGMTADDR (cfg_mgmt_addr),
    .CFGMGMTBYTEENABLE (cfg_mgmt_byte_enable),
    .CFGMGMTREAD (cfg_mgmt_read),
    .CFGMGMTTYPE1CFGREGACCESS (cfg_mgmt_type1_cfg_reg_access),
    .CFGMGMTWRITE (cfg_mgmt_write),
    .CFGMGMTWRITEDATA (cfg_mgmt_write_data),
    .CFGMSGTRANSMIT (cfg_msg_transmit),
    .CFGMSGTRANSMITDATA (cfg_msg_transmit_data),
    .CFGMSGTRANSMITTYPE (cfg_msg_transmit_type),
    .CFGPERFUNCSTATUSCONTROL (cfg_per_func_status_control),
    .CFGPERFUNCTIONNUMBER (cfg_per_function_number),
    .CFGPERFUNCTIONOUTPUTREQUEST (cfg_per_function_output_request),
    .CFGPOWERSTATECHANGEACK (cfg_power_state_change_ack),
    .CFGREQPMTRANSITIONL23READY (cfg_req_pm_transition_l23_ready),
    .CFGREVID (cfg_rev_id),
    .CFGSUBSYSID (cfg_subsys_id),
    .CFGSUBSYSVENDID (cfg_subsys_vend_id),
    .CFGTPHSTTREADDATA (cfg_tph_stt_read_data),
    .CFGTPHSTTREADDATAVALID (cfg_tph_stt_read_data_valid),
    .CFGVENDID (cfg_vend_id),
    .CFGVFFLRDONE (cfg_vf_flr_done),
    .CONFMCAPREQUESTBYCONF (conf_mcap_request_by_conf),
    .CONFREQDATA (conf_req_data),
    .CONFREQREGNUM (conf_req_reg_num),
    .CONFREQTYPE (conf_req_type),
    .CONFREQVALID (conf_req_valid),
    .CORECLK (core_clk),
    .CORECLKMICOMPLETIONRAML (core_clk),
    .CORECLKMICOMPLETIONRAMU (core_clk),
    .CORECLKMIREPLAYRAM (core_clk),
    .CORECLKMIREQUESTRAM (core_clk),
    .DBGCFGLOCALMGMTREGOVERRIDE (dbg_cfg_local_mgmt_reg_override),
    .DBGDATASEL (4'b0),
    .DRPADDR (drp_addr),
    .DRPCLK (drp_clk),
    .DRPDI (drp_di),
    .DRPEN (drp_en),
    .DRPWE (drp_we),
    .LL2LMSAXISTXTUSER (14'b0),  
    .LL2LMSAXISTXTVALID (1'b0),  
    .LL2LMTXTLPID0 (4'b0),  
    .LL2LMTXTLPID1 (4'b0),  
    .MAXISCQTREADY (m_axis_cq_tready),
    .MAXISRCTREADY (m_axis_rc_tready),
    .MCAPCLK (mcap_clk),
    .MCAPPERST0B (pcie_perstn0_in),
    .MCAPPERST1B (pcie_perstn1_in),
    .MGMTRESETN (mgmt_reset_n),
    .MGMTSTICKYRESETN (mgmt_sticky_reset_n),
    .PCIECQNPREQ (pcie_cq_np_req),
    .PIPECLK (pipe_clk),
    .PIPEEQFS (pipe_tx_eqfs),
    .PIPEEQLF (pipe_tx_eqlf),
    .PIPERESETN (pipe_reset_n),
    .PIPERX0CHARISK (pipe_rx0_char_is_k),
    .PIPERX0DATA (pipe_rx0_data),
    .PIPERX0DATAVALID (pipe_rx0_data_valid),
    .PIPERX0ELECIDLE (pipe_rx0_elec_idle),
    .PIPERX0EQDONE (pipe_rx0_eqdone),
    .PIPERX0EQLPADAPTDONE (pipe_rx0_eqlp_adaptdone),
    .PIPERX0EQLPLFFSSEL (pipe_rx0_eqlp_lffs_sel),
    .PIPERX0EQLPNEWTXCOEFFORPRESET (pipe_rx0_eqlp_new_txcoef_forpreset),
    .PIPERX0PHYSTATUS (pipe_rx0_phy_status),
    .PIPERX0STARTBLOCK (pipe_rx0_start_block),
    .PIPERX0STATUS (pipe_rx0_status),
    .PIPERX0SYNCHEADER (pipe_rx0_syncheader),
    .PIPERX0VALID (pipe_rx0_valid),
    .PIPERX1CHARISK (pipe_rx1_char_is_k),
    .PIPERX1DATA (pipe_rx1_data),
    .PIPERX1DATAVALID (pipe_rx1_data_valid),
    .PIPERX1ELECIDLE (pipe_rx1_elec_idle),
    .PIPERX1EQDONE (pipe_rx1_eqdone),
    .PIPERX1EQLPADAPTDONE (pipe_rx1_eqlp_adaptdone),
    .PIPERX1EQLPLFFSSEL (pipe_rx1_eqlp_lffs_sel),
    .PIPERX1EQLPNEWTXCOEFFORPRESET (pipe_rx1_eqlp_new_txcoef_forpreset),
    .PIPERX1PHYSTATUS (pipe_rx1_phy_status),
    .PIPERX1STARTBLOCK (pipe_rx1_start_block),
    .PIPERX1STATUS (pipe_rx1_status),
    .PIPERX1SYNCHEADER (pipe_rx1_syncheader),
    .PIPERX1VALID (pipe_rx1_valid),
    .PIPERX2CHARISK (pipe_rx2_char_is_k),
    .PIPERX2DATA (pipe_rx2_data),
    .PIPERX2DATAVALID (pipe_rx2_data_valid),
    .PIPERX2ELECIDLE (pipe_rx2_elec_idle),
    .PIPERX2EQDONE (pipe_rx2_eqdone),
    .PIPERX2EQLPADAPTDONE (pipe_rx2_eqlp_adaptdone),
    .PIPERX2EQLPLFFSSEL (pipe_rx2_eqlp_lffs_sel),
    .PIPERX2EQLPNEWTXCOEFFORPRESET (pipe_rx2_eqlp_new_txcoef_forpreset),
    .PIPERX2PHYSTATUS (pipe_rx2_phy_status),
    .PIPERX2STARTBLOCK (pipe_rx2_start_block),
    .PIPERX2STATUS (pipe_rx2_status),
    .PIPERX2SYNCHEADER (pipe_rx2_syncheader),
    .PIPERX2VALID (pipe_rx2_valid),
    .PIPERX3CHARISK (pipe_rx3_char_is_k),
    .PIPERX3DATA (pipe_rx3_data),
    .PIPERX3DATAVALID (pipe_rx3_data_valid),
    .PIPERX3ELECIDLE (pipe_rx3_elec_idle),
    .PIPERX3EQDONE (pipe_rx3_eqdone),
    .PIPERX3EQLPADAPTDONE (pipe_rx3_eqlp_adaptdone),
    .PIPERX3EQLPLFFSSEL (pipe_rx3_eqlp_lffs_sel),
    .PIPERX3EQLPNEWTXCOEFFORPRESET (pipe_rx3_eqlp_new_txcoef_forpreset),
    .PIPERX3PHYSTATUS (pipe_rx3_phy_status),
    .PIPERX3STARTBLOCK (pipe_rx3_start_block),
    .PIPERX3STATUS (pipe_rx3_status),
    .PIPERX3SYNCHEADER (pipe_rx3_syncheader),
    .PIPERX3VALID (pipe_rx3_valid),
    .PIPERX4CHARISK (pipe_rx4_char_is_k),
    .PIPERX4DATA (pipe_rx4_data),
    .PIPERX4DATAVALID (pipe_rx4_data_valid),
    .PIPERX4ELECIDLE (pipe_rx4_elec_idle),
    .PIPERX4EQDONE (pipe_rx4_eqdone),
    .PIPERX4EQLPADAPTDONE (pipe_rx4_eqlp_adaptdone),
    .PIPERX4EQLPLFFSSEL (pipe_rx4_eqlp_lffs_sel),
    .PIPERX4EQLPNEWTXCOEFFORPRESET (pipe_rx4_eqlp_new_txcoef_forpreset),
    .PIPERX4PHYSTATUS (pipe_rx4_phy_status),
    .PIPERX4STARTBLOCK (pipe_rx4_start_block),
    .PIPERX4STATUS (pipe_rx4_status),
    .PIPERX4SYNCHEADER (pipe_rx4_syncheader),
    .PIPERX4VALID (pipe_rx4_valid),
    .PIPERX5CHARISK (pipe_rx5_char_is_k),
    .PIPERX5DATA (pipe_rx5_data),
    .PIPERX5DATAVALID (pipe_rx5_data_valid),
    .PIPERX5ELECIDLE (pipe_rx5_elec_idle),
    .PIPERX5EQDONE (pipe_rx5_eqdone),
    .PIPERX5EQLPADAPTDONE (pipe_rx5_eqlp_adaptdone),
    .PIPERX5EQLPLFFSSEL (pipe_rx5_eqlp_lffs_sel),
    .PIPERX5EQLPNEWTXCOEFFORPRESET (pipe_rx5_eqlp_new_txcoef_forpreset),
    .PIPERX5PHYSTATUS (pipe_rx5_phy_status),
    .PIPERX5STARTBLOCK (pipe_rx5_start_block),
    .PIPERX5STATUS (pipe_rx5_status),
    .PIPERX5SYNCHEADER (pipe_rx5_syncheader),
    .PIPERX5VALID (pipe_rx5_valid),
    .PIPERX6CHARISK (pipe_rx6_char_is_k),
    .PIPERX6DATA (pipe_rx6_data),
    .PIPERX6DATAVALID (pipe_rx6_data_valid),
    .PIPERX6ELECIDLE (pipe_rx6_elec_idle),
    .PIPERX6EQDONE (pipe_rx6_eqdone),
    .PIPERX6EQLPADAPTDONE (pipe_rx6_eqlp_adaptdone),
    .PIPERX6EQLPLFFSSEL (pipe_rx6_eqlp_lffs_sel),
    .PIPERX6EQLPNEWTXCOEFFORPRESET (pipe_rx6_eqlp_new_txcoef_forpreset),
    .PIPERX6PHYSTATUS (pipe_rx6_phy_status),
    .PIPERX6STARTBLOCK (pipe_rx6_start_block),
    .PIPERX6STATUS (pipe_rx6_status),
    .PIPERX6SYNCHEADER (pipe_rx6_syncheader),
    .PIPERX6VALID (pipe_rx6_valid),
    .PIPERX7CHARISK (pipe_rx7_char_is_k),
    .PIPERX7DATA (pipe_rx7_data),
    .PIPERX7DATAVALID (pipe_rx7_data_valid),
    .PIPERX7ELECIDLE (pipe_rx7_elec_idle),
    .PIPERX7EQDONE (pipe_rx7_eqdone),
    .PIPERX7EQLPADAPTDONE (pipe_rx7_eqlp_adaptdone),
    .PIPERX7EQLPLFFSSEL (pipe_rx7_eqlp_lffs_sel),
    .PIPERX7EQLPNEWTXCOEFFORPRESET (pipe_rx7_eqlp_new_txcoef_forpreset),
    .PIPERX7PHYSTATUS (pipe_rx7_phy_status),
    .PIPERX7STARTBLOCK (pipe_rx7_start_block),
    .PIPERX7STATUS (pipe_rx7_status),
    .PIPERX7SYNCHEADER (pipe_rx7_syncheader),
    .PIPERX7VALID (pipe_rx7_valid),
    .PIPETX0EQCOEFF (pipe_tx0_eqcoeff),
    .PIPETX0EQDONE (pipe_tx0_eqdone),
    .PIPETX1EQCOEFF (pipe_tx1_eqcoeff),
    .PIPETX1EQDONE (pipe_tx1_eqdone),
    .PIPETX2EQCOEFF (pipe_tx2_eqcoeff),
    .PIPETX2EQDONE (pipe_tx2_eqdone),
    .PIPETX3EQCOEFF (pipe_tx3_eqcoeff),
    .PIPETX3EQDONE (pipe_tx3_eqdone),
    .PIPETX4EQCOEFF (pipe_tx4_eqcoeff),
    .PIPETX4EQDONE (pipe_tx4_eqdone),
    .PIPETX5EQCOEFF (pipe_tx5_eqcoeff),
    .PIPETX5EQDONE (pipe_tx5_eqdone),
    .PIPETX6EQCOEFF (pipe_tx6_eqcoeff),
    .PIPETX6EQDONE (pipe_tx6_eqdone),
    .PIPETX7EQCOEFF (pipe_tx7_eqcoeff),
    .PIPETX7EQDONE (pipe_tx7_eqdone),
    .PLEQRESETEIEOSCOUNT (pl_eq_reset_eieos_count),
    .PLGEN2UPSTREAMPREFERDEEMPH (pl_gen2_upstream_prefer_deemph),
    .RESETN (reset_n),
    .SPAREIN (32'b0),
    .USERCLK (user_clk),
    .CFGCURRENTSPEED (cfg_current_speed),
    .CFGDPASUBSTATECHANGE (cfg_dpa_substate_change),
    .CFGERRCOROUT (cfg_err_cor_out),
    .CFGERRFATALOUT (cfg_err_fatal_out),
    .CFGERRNONFATALOUT (cfg_err_nonfatal_out),
    .CFGEXTFUNCTIONNUMBER (cfg_ext_function_number),
    .CFGEXTREADRECEIVED (cfg_ext_read_received),
    .CFGEXTREGISTERNUMBER (cfg_ext_register_number),
    .CFGEXTWRITEBYTEENABLE (cfg_ext_write_byte_enable),
    .CFGEXTWRITEDATA (cfg_ext_write_data),
    .CFGEXTWRITERECEIVED (cfg_ext_write_received),
    .CFGFCCPLD (cfg_fc_cpld),
    .CFGFCCPLH (cfg_fc_cplh),
    .CFGFCNPD (cfg_fc_npd),
    .CFGFCNPH (cfg_fc_nph),
    .CFGFCPD (cfg_fc_pd),
    .CFGFCPH (cfg_fc_ph),
    .CFGFLRINPROCESS (cfg_flr_in_process),
    .CFGFUNCTIONPOWERSTATE (cfg_function_power_state),
    .CFGFUNCTIONSTATUS (cfg_function_status),
    .CFGHOTRESETOUT (cfg_hot_reset_out),
    .CFGINTERRUPTMSIDATA (cfg_interrupt_msi_data),
    .CFGINTERRUPTMSIENABLE (cfg_interrupt_msi_enable),
    .CFGINTERRUPTMSIFAIL (cfg_interrupt_msi_fail),
    .CFGINTERRUPTMSIMASKUPDATE (cfg_interrupt_msi_mask_update),
    .CFGINTERRUPTMSIMMENABLE (cfg_interrupt_msi_mmenable),
    .CFGINTERRUPTMSISENT (cfg_interrupt_msi_sent),
    .CFGINTERRUPTMSIVFENABLE (cfg_interrupt_msi_vf_enable),
    .CFGINTERRUPTMSIXENABLE (cfg_interrupt_msix_enable),
    .CFGINTERRUPTMSIXFAIL (cfg_interrupt_msix_fail),
    .CFGINTERRUPTMSIXMASK (cfg_interrupt_msix_mask),
    .CFGINTERRUPTMSIXSENT (cfg_interrupt_msix_sent),
    .CFGINTERRUPTMSIXVFENABLE (cfg_interrupt_msix_vf_enable),
    .CFGINTERRUPTMSIXVFMASK (cfg_interrupt_msix_vf_mask),
    .CFGINTERRUPTSENT (cfg_interrupt_sent),
    .CFGLINKPOWERSTATE (cfg_link_power_state),
    .CFGLOCALERROR (cfg_local_error),
    .CFGLTRENABLE (cfg_ltr_enable),
    .CFGLTSSMSTATE (cfg_ltssm_state),
    .CFGMAXPAYLOAD (cfg_max_payload),
    .CFGMAXREADREQ (cfg_max_read_req),
    .CFGMGMTREADDATA (cfg_mgmt_read_data),
    .CFGMGMTREADWRITEDONE (cfg_mgmt_read_write_done),
    .CFGMSGRECEIVED (cfg_msg_received),
    .CFGMSGRECEIVEDDATA (cfg_msg_received_data),
    .CFGMSGRECEIVEDTYPE (cfg_msg_received_type),
    .CFGMSGTRANSMITDONE (cfg_msg_transmit_done),
    .CFGNEGOTIATEDWIDTH (cfg_negotiated_width),
    .CFGOBFFENABLE (cfg_obff_enable),
    .CFGPERFUNCSTATUSDATA (cfg_per_func_status_data),
    .CFGPERFUNCTIONUPDATEDONE (cfg_per_function_update_done),
    .CFGPHYLINKDOWN (cfg_phy_link_down),
    .CFGPHYLINKSTATUS (cfg_phy_link_status),
    .CFGPLSTATUSCHANGE (cfg_pl_status_change),
    .CFGPOWERSTATECHANGEINTERRUPT (cfg_power_state_change_interrupt),
    .CFGRCBSTATUS (cfg_rcb_status),
    .CFGTPHFUNCTIONNUM (cfg_tph_function_num),
    .CFGTPHREQUESTERENABLE (cfg_tph_requester_enable),
    .CFGTPHSTMODE (cfg_tph_st_mode),
    .CFGTPHSTTADDRESS (cfg_tph_stt_address),
    .CFGTPHSTTREADENABLE (cfg_tph_stt_read_enable),
    .CFGTPHSTTWRITEBYTEVALID (cfg_tph_stt_write_byte_valid),
    .CFGTPHSTTWRITEDATA (cfg_tph_stt_write_data),
    .CFGTPHSTTWRITEENABLE (cfg_tph_stt_write_enable),
    .CFGVFFLRINPROCESS (cfg_vf_flr_in_process),
    .CFGVFPOWERSTATE (cfg_vf_power_state),
    .CFGVFSTATUS (cfg_vf_status),
    .CFGVFTPHREQUESTERENABLE (cfg_vf_tph_requester_enable),
    .CFGVFTPHSTMODE (cfg_vf_tph_st_mode),
    .CONFMCAPDESIGNSWITCH (conf_mcap_design_switch),
    .CONFMCAPEOS (conf_mcap_eos),
    .CONFMCAPINUSEBYPCIE (conf_mcap_in_use_by_pcie),
    .CONFREQREADY (conf_req_ready),
    .CONFRESPRDATA (conf_resp_rdata),
    .CONFRESPVALID (conf_resp_valid),
    .DBGDATAOUT (),
    .DBGMCAPCSB (dbg_mcap_cs_b),
    .DBGMCAPDATA (dbg_mcap_data),
    .DBGMCAPEOS (dbg_mcap_eos),
    .DBGMCAPERROR (dbg_mcap_errror),
    .DBGMCAPMODE (dbg_mcap_mode),
    .DBGMCAPRDATAVALID (dbg_mcap_rdata_valid),
    .DBGMCAPRDWRB (dbg_mcap_rdwr_b),
    .DBGMCAPRESET (dbg_mcap_reset),
    .DBGPLDATABLOCKRECEIVEDAFTEREDS (),
    .DBGPLGEN3FRAMINGERRORDETECTED (),
    .DBGPLGEN3SYNCHEADERERRORDETECTED (),
    .DBGPLINFERREDRXELECTRICALIDLE (),
    .DRPDO (drp_do),
    .DRPRDY (drp_rdy),
    .LL2LMMASTERTLPSENTTLPID0 (),  
    .LL2LMMASTERTLPSENTTLPID1 (),  
    .LL2LMMASTERTLPSENT0 (),  
    .LL2LMMASTERTLPSENT1 (),  
    .LL2LMMAXISRXTDATA (),  
    .LL2LMMAXISRXTUSER (),  
    .LL2LMMAXISRXTVALID (),  
    .LL2LMSAXISTXTREADY (),  
    .SAXISCCTDATA (s_axis_cc_tdata_i),
    .SAXISCCTKEEP (s_axis_cc_tkeep_i),
    .SAXISRQTDATA (s_axis_rq_tdata_i),
    .SAXISRQTKEEP (s_axis_rq_tkeep_i),
    .MAXISCQTDATA (m_axis_cq_tdata_i),
    .MAXISCQTKEEP (m_axis_cq_tkeep_i),
    .MAXISRCTDATA (m_axis_rc_tdata_i),
    .MAXISRCTKEEP (m_axis_rc_tkeep_i),
    .SAXISCCTLAST (s_axis_cc_tlast),
    .SAXISCCTUSER (s_axis_cc_tuser),
    .SAXISCCTVALID (s_axis_cc_tvalid),
    .SAXISRQTLAST (s_axis_rq_tlast),
    .SAXISRQTUSER (s_axis_rq_tuser),
    .SAXISRQTVALID (s_axis_rq_tvalid),
    .MAXISCQTLAST (m_axis_cq_tlast),
    .MAXISCQTUSER (m_axis_cq_tuser),
    .MAXISCQTVALID (m_axis_cq_tvalid),
    .MAXISRCTLAST (m_axis_rc_tlast),
    .MAXISRCTUSER (m_axis_rc_tuser),
    .MAXISRCTVALID (m_axis_rc_tvalid),
    .PCIECQNPREQCOUNT (pcie_cq_np_req_count),
    .PCIEPERST0B (pcie_perstn0_out),
    .PCIEPERST1B (pcie_perstn1_out),
    .PCIERQSEQNUM (pcie_rq_seq_num),
    .PCIERQSEQNUMVLD (pcie_rq_seq_num_vld),
    .PCIERQTAG (pcie_rq_tag),
    .PCIERQTAGAV (pcie_rq_tag_av),
    .PCIERQTAGVLD (pcie_rq_tag_vld),
    .PCIETFCNPDAV (pcie_tfc_npd_av),
    .PCIETFCNPHAV (pcie_tfc_nph_av),
    .PIPERX0EQCONTROL (pipe_rx0_eqcontrol),
    .PIPERX0EQLPLFFS (pipe_rx0_eqlp_lffs),
    .PIPERX0EQLPTXPRESET (pipe_rx0_eqlp_txpreset),
    .PIPERX0EQPRESET (pipe_rx0_eqpreset),
    .PIPERX0POLARITY (pipe_rx0_polarity),
    .PIPERX1EQCONTROL (pipe_rx1_eqcontrol),
    .PIPERX1EQLPLFFS (pipe_rx1_eqlp_lffs),
    .PIPERX1EQLPTXPRESET (pipe_rx1_eqlp_txpreset),
    .PIPERX1EQPRESET (pipe_rx1_eqpreset),
    .PIPERX1POLARITY (pipe_rx1_polarity),
    .PIPERX2EQCONTROL (pipe_rx2_eqcontrol),
    .PIPERX2EQLPLFFS (pipe_rx2_eqlp_lffs),
    .PIPERX2EQLPTXPRESET (pipe_rx2_eqlp_txpreset),
    .PIPERX2EQPRESET (pipe_rx2_eqpreset),
    .PIPERX2POLARITY (pipe_rx2_polarity),
    .PIPERX3EQCONTROL (pipe_rx3_eqcontrol),
    .PIPERX3EQLPLFFS (pipe_rx3_eqlp_lffs),
    .PIPERX3EQLPTXPRESET (pipe_rx3_eqlp_txpreset),
    .PIPERX3EQPRESET (pipe_rx3_eqpreset),
    .PIPERX3POLARITY (pipe_rx3_polarity),
    .PIPERX4EQCONTROL (pipe_rx4_eqcontrol),
    .PIPERX4EQLPLFFS (pipe_rx4_eqlp_lffs),
    .PIPERX4EQLPTXPRESET (pipe_rx4_eqlp_txpreset),
    .PIPERX4EQPRESET (pipe_rx4_eqpreset),
    .PIPERX4POLARITY (pipe_rx4_polarity),
    .PIPERX5EQCONTROL (pipe_rx5_eqcontrol),
    .PIPERX5EQLPLFFS (pipe_rx5_eqlp_lffs),
    .PIPERX5EQLPTXPRESET (pipe_rx5_eqlp_txpreset),
    .PIPERX5EQPRESET (pipe_rx5_eqpreset),
    .PIPERX5POLARITY (pipe_rx5_polarity),
    .PIPERX6EQCONTROL (pipe_rx6_eqcontrol),
    .PIPERX6EQLPLFFS (pipe_rx6_eqlp_lffs),
    .PIPERX6EQLPTXPRESET (pipe_rx6_eqlp_txpreset),
    .PIPERX6EQPRESET (pipe_rx6_eqpreset),
    .PIPERX6POLARITY (pipe_rx6_polarity),
    .PIPERX7EQCONTROL (pipe_rx7_eqcontrol),
    .PIPERX7EQLPLFFS (pipe_rx7_eqlp_lffs),
    .PIPERX7EQLPTXPRESET (pipe_rx7_eqlp_txpreset),
    .PIPERX7EQPRESET (pipe_rx7_eqpreset),
    .PIPERX7POLARITY (pipe_rx7_polarity),
    .PIPETX0CHARISK (pipe_tx0_char_is_k),
    .PIPETX0COMPLIANCE (pipe_tx0_compliance),
    .PIPETX0DATA (pipe_tx0_data),
    .PIPETX0DATAVALID (pipe_tx0_data_valid),
    .PIPETX0DEEMPH (pipe_tx0_deemph),
    .PIPETX0ELECIDLE (pipe_tx0_elec_idle),
    .PIPETX0EQCONTROL (pipe_tx0_eqcontrol),
    .PIPETX0EQDEEMPH (pipe_tx0_eqdeemph),
    .PIPETX0EQPRESET (pipe_tx0_eqpreset),
    .PIPETX0MARGIN (pipe_tx0_margin),
    .PIPETX0POWERDOWN (pipe_tx0_powerdown),
    .PIPETX0RATE (pipe_tx0_rate),
    .PIPETX0RCVRDET (pipe_tx0_rcvr_det),
    .PIPETX0RESET (pipe_tx0_reset),
    .PIPETX0STARTBLOCK (pipe_tx0_start_block),
    .PIPETX0SWING (pipe_tx0_swing),
    .PIPETX0SYNCHEADER (pipe_tx0_syncheader),
    .PIPETX1CHARISK (pipe_tx1_char_is_k),
    .PIPETX1COMPLIANCE (pipe_tx1_compliance),
    .PIPETX1DATA (pipe_tx1_data),
    .PIPETX1DATAVALID (pipe_tx1_data_valid),
    .PIPETX1DEEMPH (),  
    .PIPETX1ELECIDLE (pipe_tx1_elec_idle),
    .PIPETX1EQCONTROL (pipe_tx1_eqcontrol),
    .PIPETX1EQDEEMPH (pipe_tx1_eqdeemph),
    .PIPETX1EQPRESET (pipe_tx1_eqpreset),
    .PIPETX1MARGIN (),  
    .PIPETX1POWERDOWN (pipe_tx1_powerdown),
    .PIPETX1RATE (),  
    .PIPETX1RCVRDET (),  
    .PIPETX1RESET (),  
    .PIPETX1STARTBLOCK (pipe_tx1_start_block),
    .PIPETX1SWING (),  
    .PIPETX1SYNCHEADER (pipe_tx1_syncheader),
    .PIPETX2CHARISK (pipe_tx2_char_is_k),
    .PIPETX2COMPLIANCE (pipe_tx2_compliance),
    .PIPETX2DATA (pipe_tx2_data),
    .PIPETX2DATAVALID (pipe_tx2_data_valid),
    .PIPETX2DEEMPH (),  
    .PIPETX2ELECIDLE (pipe_tx2_elec_idle),
    .PIPETX2EQCONTROL (pipe_tx2_eqcontrol),
    .PIPETX2EQDEEMPH (pipe_tx2_eqdeemph),
    .PIPETX2EQPRESET (pipe_tx2_eqpreset),
    .PIPETX2MARGIN (),  
    .PIPETX2POWERDOWN (pipe_tx2_powerdown),
    .PIPETX2RATE (),  
    .PIPETX2RCVRDET (),  
    .PIPETX2RESET (),  
    .PIPETX2STARTBLOCK (pipe_tx2_start_block),
    .PIPETX2SWING (),  
    .PIPETX2SYNCHEADER (pipe_tx2_syncheader),
    .PIPETX3CHARISK (pipe_tx3_char_is_k),
    .PIPETX3COMPLIANCE (pipe_tx3_compliance),
    .PIPETX3DATA (pipe_tx3_data),
    .PIPETX3DATAVALID (pipe_tx3_data_valid),
    .PIPETX3DEEMPH (),  
    .PIPETX3ELECIDLE (pipe_tx3_elec_idle),
    .PIPETX3EQCONTROL (pipe_tx3_eqcontrol),
    .PIPETX3EQDEEMPH (pipe_tx3_eqdeemph),
    .PIPETX3EQPRESET (pipe_tx3_eqpreset),
    .PIPETX3MARGIN (), 
    .PIPETX3POWERDOWN (pipe_tx3_powerdown),
    .PIPETX3RATE (), 
    .PIPETX3RCVRDET (), 
    .PIPETX3RESET (), 
    .PIPETX3STARTBLOCK (pipe_tx3_start_block),
    .PIPETX3SWING (), 
    .PIPETX3SYNCHEADER (pipe_tx3_syncheader),
    .PIPETX4CHARISK (pipe_tx4_char_is_k),
    .PIPETX4COMPLIANCE (pipe_tx4_compliance),
    .PIPETX4DATA (pipe_tx4_data),
    .PIPETX4DATAVALID (pipe_tx4_data_valid),
    .PIPETX4DEEMPH (), 
    .PIPETX4ELECIDLE (pipe_tx4_elec_idle),
    .PIPETX4EQCONTROL (pipe_tx4_eqcontrol),
    .PIPETX4EQDEEMPH (pipe_tx4_eqdeemph),
    .PIPETX4EQPRESET (pipe_tx4_eqpreset),
    .PIPETX4MARGIN (), 
    .PIPETX4POWERDOWN (pipe_tx4_powerdown),
    .PIPETX4RATE (), 
    .PIPETX4RCVRDET (), 
    .PIPETX4RESET (), 
    .PIPETX4STARTBLOCK (pipe_tx4_start_block),
    .PIPETX4SWING (), 
    .PIPETX4SYNCHEADER (pipe_tx4_syncheader),
    .PIPETX5CHARISK (pipe_tx5_char_is_k),
    .PIPETX5COMPLIANCE (pipe_tx5_compliance),
    .PIPETX5DATA (pipe_tx5_data),
    .PIPETX5DATAVALID (pipe_tx5_data_valid),
    .PIPETX5DEEMPH (),
    .PIPETX5ELECIDLE (pipe_tx5_elec_idle),
    .PIPETX5EQCONTROL (pipe_tx5_eqcontrol),
    .PIPETX5EQDEEMPH (pipe_tx5_eqdeemph),
    .PIPETX5EQPRESET (pipe_tx5_eqpreset),
    .PIPETX5MARGIN (), 
    .PIPETX5POWERDOWN (pipe_tx5_powerdown),
    .PIPETX5RATE (), 
    .PIPETX5RCVRDET (),
    .PIPETX5RESET (), 
    .PIPETX5STARTBLOCK (pipe_tx5_start_block),
    .PIPETX5SWING (), 
    .PIPETX5SYNCHEADER (pipe_tx5_syncheader),
    .PIPETX6CHARISK (pipe_tx6_char_is_k),
    .PIPETX6COMPLIANCE (pipe_tx6_compliance),
    .PIPETX6DATA (pipe_tx6_data),
    .PIPETX6DATAVALID (pipe_tx6_data_valid),
    .PIPETX6DEEMPH (), 
    .PIPETX6ELECIDLE (pipe_tx6_elec_idle),
    .PIPETX6EQCONTROL (pipe_tx6_eqcontrol),
    .PIPETX6EQDEEMPH (pipe_tx6_eqdeemph),
    .PIPETX6EQPRESET (pipe_tx6_eqpreset),
    .PIPETX6MARGIN (), 
    .PIPETX6POWERDOWN (pipe_tx6_powerdown),
    .PIPETX6RATE (),
    .PIPETX6RCVRDET (),
    .PIPETX6RESET (), 
    .PIPETX6STARTBLOCK (pipe_tx6_start_block),
    .PIPETX6SWING (), 
    .PIPETX6SYNCHEADER (pipe_tx6_syncheader),
    .PIPETX7CHARISK (pipe_tx7_char_is_k),
    .PIPETX7COMPLIANCE (pipe_tx7_compliance),
    .PIPETX7DATA (pipe_tx7_data),
    .PIPETX7DATAVALID (pipe_tx7_data_valid),
    .PIPETX7DEEMPH (), 
    .PIPETX7ELECIDLE (pipe_tx7_elec_idle),
    .PIPETX7EQCONTROL (pipe_tx7_eqcontrol),
    .PIPETX7EQDEEMPH (pipe_tx7_eqdeemph),
    .PIPETX7EQPRESET (pipe_tx7_eqpreset),
    .PIPETX7MARGIN (), 
    .PIPETX7POWERDOWN (pipe_tx7_powerdown),
    .PIPETX7RATE (), 
    .PIPETX7RCVRDET (), 
    .PIPETX7RESET (), 
    .PIPETX7STARTBLOCK (pipe_tx7_start_block),
    .PIPETX7SWING (), 
    .PIPETX7SYNCHEADER (pipe_tx7_syncheader),
    .PLEQINPROGRESS (pl_eq_in_progress),
    .PLEQPHASE (pl_eq_phase),
    .SAXISCCTREADY (s_axis_cc_tready),
    .SAXISRQTREADY (s_axis_rq_tready),
    .SPAREOUT ()
  );

//
//

endmodule
